參數(shù)資料
型號: ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù): 63/102頁
文件大?。?/td> 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
63 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
8
PPS
On read
—PortPowerStatus:
This bit reflects the port power
status, regardless of the type of power switching implemented.
This bit is cleared if an overcurrent condition is detected. The HCD
can set this bit by writing SetPortPower or SetGlobalPower. The
HCD can clear this bit by writing ClearPortPower or
ClearGlobalPower. PowerSwitchingMode and
PortPowerControlMask[NDP] determine which power control
switches are enabled. In the global switching mode
(PowerSwitchingMode = 0), only Set/ClearGlobalPower controls
this bit. In the per-port power switching
(PowerSwitchingMode = 1), if the PortPowerControlMask[NDP] bit
for the port is set, only Set/ClearPortPower commands are
enabled. If the mask is not set, only Set/ClearGlobalPower
commands are enabled.
When port power is disabled, CCS (CurrentConnectStatus), PES
(PortEnableStatus), PSS (PortSuspendStatus) and PRS
(PortResetStatus) should be reset.
0 —
port power is OFF
1 —
port power is ON
On write—
SetPortPower:
The HCD can write logic 1 to set the
PPS (PortPowerStatus) bit. Writing logic 0 has no effect.
Remark:
This bit always reads logic1 if power switching is not
supported.
reserved
On read—
PortResetStatus:
When this bit is set by a write to
SetPortReset, port reset signaling is asserted. When reset is
completed and PRSC (PortResetStatusChange) is set, this bit is
cleared.
7 to 5
4
-
PRS
0 —
port reset signal is not active
1 —
port reset signal is active
On write—
SetPortReset:
The HCD can set the port reset
signaling by writing a 1 to this bit. Writing a 0 has no effect. If CCS
is cleared, this write does not set PRS (PortResetStatus) but
instead sets CCS. This informs the driver that it attempted to reset
a disconnected port.
On read—
PortOverCurrentIndicator:
This bit is valid only when
the Root Hub is configured to show overcurrent conditions are
reported on a per-port basis. If the per-port overcurrent reporting is
not supported, this bit is set to logic 0. If cleared, all power
operations are normal for this port. If set, an overcurrent condition
exists on this port.
3
POCI
0 —
no overcurrent condition
1 —
overcurrent condition detected
On write—
ClearSuspendStatus:
The HCD can write logic 1 to
initiate a resume. Writing logic 0 has no effect. A resume is
initiated only if PSS (PortSuspendStatus) is set.
Table 85:
Bit
HCRhPortStatus[1:4] register: bit description
…continued
Symbol
Description
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