參數資料
型號: ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數: 76/102頁
文件大小: 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
76 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Bit
Symbol
7
6
5
4
3
2
1
0
reserved
IAA
HSE
FLR
PCD
USB
ERRINT
0
R/W
USBINT
Reset
Access
0
-
0
-
0
R
0
0
0
0
R/W
R/W
R/W
R/W
Table 105: USBSTS register: bit description
Bit
Symbol
31 to 16
-
15
ASS
Description
reserved
Asynchronous Schedule Status
: 0 = Default. The bit reports
the current real status of the Asynchronous Schedule. If this bit is
zero, the status of the Asynchronous Schedule is disabled. If this
bit is one, the status of the Asynchronous Schedule is enabled.
The Host Controller is not required to immediately disable or
enable the Asynchronous Schedule when software changes the
ASE (Asynchronous Schedule Enable) bit in the USBCMD
register. When this bit and the ASE (Asynchronous Schedule
Enable) bit are the same value, the Asynchronous Schedule is
either enabled (1) or disabled (0).
Periodic Schedule Status
: 0 = Default. This bit reports the
current status of the Periodic Schedule. If this bit is zero then the
status of the Periodic Schedule is disabled. If this bit is a one
then the status of the Periodic Schedule is enabled. The Host
Controller is not required to immediately disable or enable the
Periodic Schedule when software changes the PSE (Periodic
Schedule Enable) bit in the USBCMD register. When this bit and
the PSE bit are the same value, the Periodic Schedule is either
enabled (1) or disabled (0).
Reclamation
: 0 = Default. This is a read-only status bit that is
used to detect an empty asynchronous schedule.
HCHalted
: 1 = Default. This bit is zero when the Run/Stop bit of
the USBCMD register is one. The Host Controller sets this bit to
one after it has stopped executing as a result of the Run/Stop bit
being set to zero, either by software or by the Host Controller
hardware (for example, on an internal error).
reserved
Interrupt on Asynchronous Advance
: 0 = Default. System
software can force the Host Controller to issue an interrupt the
next time the Host Controller advances the asynchronous
schedule by writing a one to the IAAD (Interrupt on
Asynchronous Advance Doorbell) bit in the USBCMD register.
This status bit indicates the assertion of that interrupt source.
Host System Error
: The Host Controller sets this bit when a
serious error occurs during a host system access involving the
Host Controller module. In a PCI system, conditions that set this
bit include PCI Parity error, PCI Master Abort and PCI Target
Abort. When this error occurs, the Host Controller clears the RS
(Run/Stop) bit in the USBCMD register to prevent further
execution of the scheduled TDs.
14
PSSTAT
13
RECL
12
HCH
11 to 6
5
-
IAA
4
HSE
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