參數(shù)資料
型號(hào): ISP1561BM
廠(chǎng)商: NXP SEMICONDUCTORS
元件分類(lèi): 總線(xiàn)控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁(yè)數(shù): 26/102頁(yè)
文件大?。?/td> 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
26 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
EHCI Host Controller. The system-specific policy can be established by BIOS
initializing this register to a system-specific value. System software uses the
information in this register when enabling devices and ports for remote wake-up.
8.2.3
Power management registers
Cap_ID register (address: value read from address 34H + 0H):
The Capability
Identifier (Cap_ID) register, when read by the system software as 01H indicates that
the data structure currently being pointed to is the PCI Power Management data
structure. Each function of a PCI device may have only one item in its capability list
with Cap_ID set to 01H. The bit description o the register is given in
Table 31
.
Next_Item_Ptr register (address: value read from address 34H + 1H):
The Next
Item Pointer (Next_Item_Ptr) register (see
Table 32
) describes the location of the next
item in the function’s capability list. The value given is an offset into the function’s PCI
Configuration Space. If the function does not implement any other capabilities
defined by the PCI-SIG for inclusion in the capabilities list, or if power management is
the last item in the list, then this register must be set to 00H.
PMC register (address: value read from address 34H
+
2H):
The Power
Management Capabilities (PMC) register is a two-byte register, and the bit allocation
is given in
Table 33
. This read-only register provides information on the capabilities of
the function related to power management.
Table 29:
Bit
15 to 0
PORTWAKECAP register: bit description
Symbol
PORTWAKECAP[15:0]
Access
R/W
Value
001FH
Port Wake Up Capability Mask
: EHCI does not implement this
feature.
Description
Table 30:
Offset
value read from address 34H + 0H
value read from address 34H + 1H
value read from address 34H + 2H
value read from address 34H + 4H
value read from address 34H + 6H
value read from address 34H + 7H
Power Management registers
Register
Capability Identifier (Cap_ID)
Next Item Pointer (Next_Item_Ptr)
Power Management Capabilities (PMC)
Power Management Control/Status (PMCSR)
Power Management Control/Status (PMCSR_BSE)
Data
Table 31:
Bit
7 to 0
Cap_ID register: bit description
Symbol
Access
Cap_ID[7:0]
R
Value
01H
Description
ID
: This field when 01H identifies the linked list item as being the
PCI Power Management registers.
Table 32:
Bit
7 to 0
Next_Item_Ptr register: bit description
Symbol
Next_Item_Ptr[7:0]
Access
R
Value
00H
Description
Next Item Pointer
: This field provides an offset into the function’s PCI
Configuration Space pointing to the location of the next item in the
function’s capability list. If there are no additional items in the
Capabilities List, this register is set to 00H.
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