參數(shù)資料
型號: ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù): 66/102頁
文件大小: 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
66 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11.2.2
HceInput register (address: value read from func0 or func1 of address
10H + 104H)
The HceInput register is a four-byte register, and the bit allocation is given in
Table 90
. I/O data that is written to ports 60H and 64H is captured in this register
when emulation is enabled. This register may be read or written directly by accessing
it in the Host Controller’s operational register space. When accessed directly in a
memory cycle, reads and writes of this register have no side effects.
Table 89:
Bit
31 to 9
8
HceControl register: bit description
Symbol
-
A20S
Description
reserved
A20State
: This bit indicates the current state of Gate A20
on the keyboard controller. It is used to compare against
value written to 60H when GA20S (GateA20Sequence) is
active.
IRQ12Active
: This bit indicates that a positive transition
on IRQ12 from the keyboard controller has occurred.
Writing a logic 1 sets IRQ12 to logic 0 (inactive). Writing a
logic 0 to this bit has no effect.
IRQ1Active
: This bit indicates that a positive transition on
IRQ1 from the keyboard controller has occurred.
Writing a logic 1 sets IRQ1 to logic 0 (inactive). Writing a
logic 0 to this bit has no effect.
GateA20Sequence
: This bit is set by the Host Controller
when a data value of D1H is written to I/O port 64H and
cleared, on a write to I/O port 64H of any value other than
D1H.
ExternalIRQEn
: When this bit is set to logic 1, IRQ1 and
IRQ12 from the keyboard controller cause an emulation
interrupt. This bit is independent of the setting of the EE
(EmulationEnable) bit in this register.
IRQEn
: When this bit is set, the Host Controller generates
IRQ1 or IRQ12 as long as the OUT_FULL (OutputFull) bit
in HceStatus is set to logic 1. If the AUX_OUT_FULL
(AuxOutputFull) bit of HceStatus is logic 0, then IRQ1 is
generated; if it is logic 1, then an IRQ12 is generated.
CharacterPending
: When this bit is set, an emulation
interrupt is generated when the OUT_FULL (OutputFull)
bit of the HceStatus register is set to logic 0.
EmulationInterrupt
: This bit shows the emulation
interrupt condition.
7
IRQ12A
6
IRQ1A
5
GA20S
4
EIRQEn
3
IRQEn
2
C_P
1
EI
logic 0 —
legacy emulation enabled
logic 1 —
legacy emulation disabled
EmulationEnable
: When this bit is set to logic 1, the Host
Controller is enabled for legacy emulation. The Host
Controller decodes accesses to I/O registers 60H and
64H and enables interrupts on IRQ1 and/or IRQ12. The
Host Controller also generates an emulation interrupt at
appropriate times to invoke the emulation software.
0
EE
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