參數(shù)資料
型號(hào): ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù): 42/102頁
文件大?。?/td> 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
42 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11.1.4
HcInterruptStatus register (address: value read from func0 or func1 of address
10H
+
0CH)
This register is a four-byte register that provides the status of the events that cause
hardware interrupts. The bit allocation of the register is given in
Table 48
. When an
event occurs, the Host Controller sets the corresponding bit in this register. When a
bit becomes set, a hardware interrupt is generated if the interrupt is enabled in the
HcInterruptEnable register (see
Table 50
) and the MIE (MasterInterruptEnable) bit is
set. The HCD may clear specific bits in this register by writing logic 1 to the bit
positions to be cleared. The HCD may not set any of these bits. The Host Controller
does not clear the bit.
2
BLF
BulkListFilled
: This bit is used to indicate whether there are any
Transfer Descriptors (TDs) on the Bulk list. It is set by the HCD
whenever it adds a TD to an ED in the Bulk list. When the Host
Controller begins to process the head of the Bulk list, it checks
bulk-filled (BF). If BLF (BulkListFilled) is logic 0, the Host Controller
does not need to process the Bulk list. If BLF is logic 1, the Host
Controller needs to start processing the Bulk list and set BF to
logic 0. If the Host Controller finds a TD on the list, then the Host
Controller needs to set BLF to logic 1 causing the Bulk list
processing to continue. If no TD is found on the Bulk list, and if the
HCD does not set BLF, then BLF is still logic 0 when the Host
Controller completes processing the Bulk list and the Bulk list
processing stops.
ControlListFilled
: This bit is used to indicate whether there are
any TDs on the Control list. It is set by the HCD whenever it adds a
TD to an ED in the Control list.
When the Host Controller begins to process the head of the
Control list, it checks ControlListFilled (CLF). If CLF is logic 0, the
Host Controller does not need to process the Control list. If
control-filled (CF) is logic 1, the Host Controller needs to start
processing the Control list and set CLF to logic 0. If the Host
Controller finds a TD on the list, then the Host Controller needs to
set CLF to logic 1 causing the Control list processing to continue. If
no TD is found on the Control list, and if the HCD does not set CLF,
then CLF is still logic 0 when the Host Controller completes
processing the Control list and the Control list processing stops.
HostControllerReset:
This bit is set by the HCD to initiate a
software reset of the Host Controller. Regardless of the functional
state of the Host Controller, it moves to the USBSUSPEND state in
which most of the operational registers are reset except those
stated otherwise; for example, the IR (InterruptRouting) field of
HcControl, and no Host bus accesses are allowed. This bit is
cleared by the Host Controller upon the completion of the reset
operation. The reset operation must be completed within 10
μ
s.
This bit, when set, should not cause a reset to the Root Hub and
no subsequent reset signaling should be asserted to its
downstream ports.
1
CLF
0
HCR
Table 47:
Bit
HcCommandStatus register: bit description
…continued
Symbol
Description
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