參數(shù)資料
型號: ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù): 62/102頁
文件大?。?/td> 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
62 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
18
PSSC
PortSuspendStatusChange:
This bit is set when the full resume
sequence has been completed. This sequence includes the 20 ms
resume pulse, LS EOP and 3 ms re-synchronization delay. The
HCD can write logic 1 to clear this bit. Writing logic 0 has no effect.
This bit is also cleared when ResetStatusChange is set.
0 —
resume is not completed
1 —
resume is completed
PortEnableStatusChange:
This bit is set when hardware events
cause the PES (PortEnableStatus) bit to be cleared. Changes from
the HCD writes do not set this bit. The HCD can write logic 1 to
clear this bit. Writing logic 0 has no effect.
17
PESC
0 —
no change in PES
1 —
change in PES
ConnectStatusChange:
This bit is set whenever a connect or
disconnect event occurs. The HCD can write logic 1 to clear this
bit. Writing logic 0 has no effect. If CCS (CurrentConnectStatus) is
cleared when a SetPortReset, SetPortEnable or SetPortSuspend
write occurs, this bit is set to force the driver to re-evaluate the
connection status because these writes should not occur if the port
is disconnected.
16
CSC
0 —
no change in CCS
1 —
change in CCS
Remark:
If the DeviceRemovable[NDP] bit is set, this bit is set only
after a Root Hub reset to inform the system that the device is
attached.
reserved
On read—
LowSpeedDeviceAttached:
This bit indicates the
speed of the device attached to this port. When set, a low-speed
device is attached to this port. When clear, a full-speed device is
attached to this port. This field is valid only when the CCS is set.
15 to 10
9
-
LSDA
0 —
port is not suspended
1 —
port is suspended
On write—
ClearPortPower:
The HCD can clear the PPS
(PortPowerStatus) bit by writing logic 1 to this bit. Writing logic 0
has no effect.
Table 85:
Bit
HCRhPortStatus[1:4] register: bit description
…continued
Symbol
Description
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