參數(shù)資料
型號: ISP1161BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 64/127頁
文件大?。?/td> 2762K
代理商: ISP1161BM
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
64 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
Code (Hex): 0E —
read
13.2.3
HcFmNumber Register
The HcFmNumber register is a 16-bit counter. It provides a timing reference for
events happening in the HC and the HCD. The HCD may use the 16-bit value
specified in this register and generate a 32-bit frame number without requiring
frequent access to the register.
Table 31: HcFmRemaining Register: bit description
Bit
Symbol
Description
31
FRT
FrameRemainingToggle:
This bit is loaded from the
FrameIntervalToggle field of HcFmInterval whenever
FrameRemaining reaches 0. This bit is used by the Host Controller
Driver (HCD) for synchronization between FrameInterval and
FrameRemaining.
30 to 14
-
reserved
13 to 0
FR[13:0]
FrameRemaining:
This counter is decremented at each bit time.
When it reaches zero, it is reset by loading the FrameInterval value
specified in HcFmInterval at the next bit time boundary. When
entering the USBOPERATIONAL state, the HC reloads it with the
content of the FrameInterval part of the HcFmInterval register and
uses the updated value from the next SOF.
Table 32: HCFmNumber Register: bit allocation
Bit
31
Symbol
Reset
Access
Bit
23
Symbol
Reset
Access
Bit
15
Symbol
Reset
0
Access
Bit
7
Symbol
Reset
0
Access
30
29
28
27
26
25
24
reserved
00H
R
22
21
20
19
18
17
16
reserved
00H
R
14
13
12
11
10
9
8
FN[15:8]
0
0
0
0
0
0
0
R
6
5
4
3
2
1
0
FN[7:0]
0
0
0
0
0
0
0
R
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