參數(shù)資料
型號： ISP1161BM
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Full-speed Universal Serial Bus single-chip host and device controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù)： 103/127頁
文件大?。?/td> 2762K
代理商： ISP1161BM
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
103 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
14.3.6
Read Interrupt Register
This command indicates the sources of interrupts as stored in the 4-byte Interrupt
Register. Each individual endpoint has its own interrupt bit. The bit allocation of the
Interrupt Register is shown in
Table 106
. Bit BUSTATUS is used to verify the current
bus status in the interrupt service routine. Interrupts are enabled via the Interrupt
Enable Register, see
Section 14.1.5
.
While reading the interrupt register, please read both 2 bytes completely.
Code (Hex): C0 —
read interrupt register
Transaction —
read 2 words
Table 105:Chip ID Register: bit description
Bit
Symbol
15 to 8
CHIPIDH[7:0]
7 to 0
CHIPIDL[7:0]
Description
chip ID code (61H)
silicon version (XXH, with XX representing the BCD encoded
version number)
Table 106:Interrupt Register: bit allocation
Bit
31
Symbol
reserved
Reset
0
Access
R
Bit
23
Symbol
EP14
Reset
0
Access
R
Bit
15
Symbol
EP6
Reset
0
Access
R
Bit
7
Symbol
BUSTATUS
Reset
0
Access
R
30
29
28
27
26
25
24
reserved
0
R
22
EP13
0
R
14
EP5
0
R
6
reserved
0
R
reserved
0
R
21
EP12
0
R
13
EP4
0
R
5
PSOF
0
R
reserved
0
R
20
EP11
0
R
12
EP3
0
R
4
SOF
0
R
reserved
0
R
19
EP10
0
R
11
EP2
0
R
3
EOT
0
R
reserved
0
R
18
EP9
0
R
10
EP1
0
R
2
SUSPND
0
R
reserved
0
R
17
EP8
0
R
9
EP0IN
0
R
1
RESUME
0
R
reserved
0
R
16
EP7
0
R
8
EP0OUT
0
R
0
RESET
0
R
Table 107: Interrupt Register: bit description
Bit
Symbol
31 to 24
-
23 to 10
EP14 to EP1
9
EP0IN
8
EP0OUT
7
BUSTATUS
6
-
Description
reserved
A logic 1 indicates the interrupt source(s): endpoint 14 to 1
A logic 1 indicates the interrupt source: control IN endpoint
A logic 1 indicates the interrupt source: control OUT endpoint
Monitors the current USB bus status (0 = awake, 1 = suspend).
reserved
相關(guān)PDF資料
PDF描述
ISP1181ABS INDUCTOR 1.0NH +-.3NH FIXED SMD
ISP1181A Full-speed Universal Serial Bus peripheral controller
ISP1181ADGG Full-speed Universal Serial Bus peripheral controller
ISP1181B Full-speed Universal Serial Bus peripheral controller
ISP1181BBS Full-speed Universal Serial Bus peripheral controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1181 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device
ISP1181A 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller
ISP1181ABS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller
ISP1181ABS,518 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1181ABS,551 功能描述:USB 接口集成電路 USB 1.1 ADVANCED DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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