參數(shù)資料
型號(hào): ISP1161BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 118/127頁
文件大小: 2762K
代理商: ISP1161BM
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
118 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
21.2 Interfacing a ISP1161 with a SH7709 RISC processor
This section shows a typical interface circuit between ISP1161 and a RISC
processor. The Hitachi SH-3 series RISC processor SH7709 is used as the example.
The main ISP1161 signals to be taken into consideration for connecting to a SH7709
RISC processor are:
A 16-bit data bus: D15-D0 for ISP1161. ISP1161 is ‘little endian‘ compatible.
Two address lines A1 and A0 are needed for a complete addressing of the
ISP1161 internal registers:
A1 = 0 and A0 = 0 will select the Data Port of the Host Controller
A1 = 0 and A0 = 1 will select the Command Port of the Host Controller
A1 = 1 and A0 = 0 will select the Data Port of the Device Controller
A1 = 1 and A0 = 1 will select the Command Port of the Device Controller
The CS line is used for chip selection of ISP1161 in a certain address range of the
RISC system. This signal is active LOW.
RD and WR are common read and write signals. These signals are active LOW.
There are two DMA channel standard control lines:
DREQ1 and DACK1
DREQ2 and DACK2
(in each case one channel is used by the host controller and the other channel is
used by the device controller). These signals have programmable active levels.
Two interrupt lines: INT1 (used by the host controller) and INT2 (used by the
device controller). Both have programmable level/edge and polarity (active HIGH
or LOW).
The internal 15k
pull-down resistors are used for the HCs two USB downstream
ports.
The RESET signal is active LOW.
Remark:
SH7709’s system clock input is for reference only. Please refer to SH7709’s
specification for its actual use.
ISP1161 can work under either +3.3 V or +5.0 V power supply; however, its internal
core actually works at +3.3 V. When using +5 V as the power supply input, the
internal DC/DC regulator will be bypassed. It is best to connect all four power supply
pins (V
CC
, V
reg(3.3)
, V
hold1
and V
hold2
) to the 3.3 V power supply (for more information
see
Section 16
). All of the ISP1161’s I/O pins are +5 V-tolerant. This feature allows
the ISP1161 the flexibility to be used in an embedded system under either a +3.3 V or
a +5 V power supply.
A typical SH7709 interface circuit is shown in
Figure 55
.
21.3 Typical software model
This section shows a typical software requirement for an embedded system that
incorporates ISP1161. The software model for a digital still camera (DSC) is used as
the example for illustration (as shown in
Figure 56
). Two components of system
software are required to make full use of the features in ISP1161: the host stack and
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