參數(shù)資料
型號： ISP1161BM
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Full-speed Universal Serial Bus single-chip host and device controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù)： 20/127頁
文件大小： 2762K
代理商： ISP1161BM
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
20 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
The interrupt events of the Hc
μ
PInterrupt register (24H - Read, A4H - Write) changes
the status of pin INT1 when the corresponding bits of the Hc
μ
PInterruptEnable
register (25H - Read, A5H - Write) and pin INT1’s global enable bit (bit 0 of the
HcHardwareConfiguration register) are all set to enable status.
However, events that come from the HcInterruptStatus register (03H - Read, 83H -
Write) affect only the OPR_Reg bit of the Hc
μ
PInterrupt register. They cannot directly
change the status of pin INT1.
8.6.3
DC’s interrupt output pin (INT2)
The DC’s interrupt output pin INT2’s four configuration modes can also be
programmed by setting bit 0 (INTPOL) and bit 1 (INTLVL) of the DC’s hardware
configuration register (BBH - Read, BAH - Write). Bit 3 (INTENA) of the DC’s mode
register (B9H - Read, B8H - Write) is used as pin INT2’s global enable setting.
Figure 22
shows the relationship between the interrupt events and pin INT2.
Each of the indicated USB events is logged in a status bit of the Interrupt Register.
Corresponding bits in the Interrupt Enable Register determine whether or not an
event will generate an interrupt.
Interrupts can be masked globally by means of the INTENA bit of the Mode Register
(see
Table 80
).
The active level and signalling mode of the INT output is controlled by the INTPOL
and INTLVL bits of the Hardware Configuration Register (see
Table 82
). Default
settings after reset are active LOW and level mode. When pulse mode is selected, a
pulse of 166 ns is generated when the OR-ed combination of all interrupt bits
changes from logic 0 to logic 1.
Fig 21. HC interrupt logic.
MGT945
SOF/ITL
ATL
All EOT
OPR Reg
HcSuspend
HcuPInterrupt
register
HcuPInterruptEnable
register
HcInterruptStatus
register
HcInterruptEnable
register
ClkReady
SOF/ITL IE
ATL IE
All EOT IE
OPR Reg IE
HcSuspend IE
ClkReady IE
SO
SF
RD
UE
FNO
RHSC
SO IE
SF IE
RD IE
UE IE
FNO IE
RHSC IE
INT Enable
INT Trigger
INT Polarity
HcHardwareConfiguration
register
PULSE
GENERATOR
INT1
1
0
X
X
相關(guān)PDF資料
PDF描述
ISP1181ABS INDUCTOR 1.0NH +-.3NH FIXED SMD
ISP1181A Full-speed Universal Serial Bus peripheral controller
ISP1181ADGG Full-speed Universal Serial Bus peripheral controller
ISP1181B Full-speed Universal Serial Bus peripheral controller
ISP1181BBS Full-speed Universal Serial Bus peripheral controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1181 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device
ISP1181A 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller
ISP1181ABS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller
ISP1181ABS,518 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1181ABS,551 功能描述:USB 接口集成電路 USB 1.1 ADVANCED DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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