參數(shù)資料
型號(hào): ISP1161ABM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 99/134頁
文件大小: 587K
代理商: ISP1161ABM
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
99 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13.1.8
Reset Device (F6H)
This command resets the ISP1161A DC in the same way as an external hardware
reset via input RESET. All registers are initialized to their ‘reset’ values.
Code (Hex): F6 —
reset the device
Transaction —
none
13.2 Data flow commands
Data flow commands are used to manage the data transmission between the USB
endpoints and the system microprocessor. Much of the data flow is initiated via an
interrupt to the microprocessor. The data flow commands are used to access the
endpoints and determine whether the endpoint FIFOs contain valid data.
Remark:
The IN buffer of an endpoint contains input data
for
the host, the OUT buffer
receives output data
from
the host.
13.2.1
Write/Read Endpoint Buffer (R/W: 10H,12H-1FH/01H–0FH)
This command is used to access endpoint FIFO buffers for reading or writing. First,
the buffer pointer is reset to the beginning of the buffer. Following the command, a
maximum of (M + 1) words can be written or read, with M given by (N
+
1) DIV 2, N
representing the size of the endpoint buffer. After each read/write action the buffer
pointer is automatically incremented by 2.
In DMA access, the first word (the packet length) is skipped: transfers start at the
second word of the endpoint buffer. When reading, the ISP1161A DC can detect the
last word via the End of Packet (EOP) condition. When writing to a bulk/interrupt
endpoint, the endpoint buffer must be completely filled before sending the data to the
host. Exception: when a DMA transfer is stopped by an external EOT condition, the
current buffer content (full or not) is sent to the host.
Remark:
Reading data after a Write Endpoint Buffer command or writing data after a
Read Endpoint Buffer command will cause unpredictable behavior of the ISP1161A
DC.
Code (Hex): 01 to 0F —
write (control IN, endpoint 1 to 14)
Code (Hex): 10, 12 to 1F —
read (control OUT, endpoint 1 to 14)
Transaction —
write/read maximum (M + 1) words (isochronous endpoint: N
1023,
bulk/interrupt endpoint: N
32)
The data in the endpoint FIFO must be organized as shown in
Table 90
. An example
of endpoint FIFO access is given
Table 91
.
Table 89:
Bit
15 to 0
DcDMACounter register: bit description
Symbol
Description
DMACR[15:0]
DMA Counter register
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