參數(shù)資料
型號： ISP1161ABM
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Full-speed Universal Serial Bus single-chip host and device controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù)： 50/134頁
文件大?。?/td> 587K
代理商： ISP1161ABM
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
50 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.1.6
HcInterruptDisable register (R/W: 05H/85H)
Each disable bit in the HcInterruptDisable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is
coupled with the HcInterruptEnable register. Thus, writing logic 1 to a bit in this
register clears the corresponding bit in the HcInterruptEnable register, whereas
Table 16:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterruptEnable register: bit allocation
31
30
MIE
0
0
R/W
R/W
23
22
29
28
27
26
25
24
reserved
0
R/W
19
0
0
0
0
0
R/W
21
R/W
20
R/W
18
R/W
17
R/W
16
reserved
0
0
0
0
0
0
0
0
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
0
0
0
0
0
0
0
0
R/W
7
R/W
6
RHSC
0
R/W
R/W
5
FNO
0
R/W
R/W
4
UE
0
R/W
R/W
3
RD
0
R/W
R/W
2
SF
0
R/W
R/W
1
R/W
0
SO
0
R/W
reserved
0
R/W
reserved
0
R/W
Table 17:
Bit
31
HcInterruptEnable register: bit description
Symbol
Description
MIE
MasterInterruptEnable
by the HCD: Logic 0 is ignored by the HC.
Logic 1 enables interrupt generation by events specified in other
bits of this register.
-
reserved
RHSC
0 —
ignore
30 to 7
6
1 —
enable interrupt generation due to Root Hub Status Change
0 —
ignore
5
FNO
1 —
enable interrupt generation due to Frame Number Overflow
0 —
ignore
4
UE
1 —
enable interrupt generation due to Unrecoverable Error
0 —
ignore
3
RD
1 —
enable interrupt generation due to Resume Detect
0 —
ignore
2
SF
1 —
enable interrupt generation due to Start of Frame
reserved
0 —
ignore
1
0
-
SO
1 —
enable interrupt generation due to Scheduling Overrun
相關(guān)PDF資料
PDF描述
ISP1161 Full-speed Universal Serial Bus single-chip host and device controller
ISP1161A1 Universal Serial Bus single-chip host and device controller
ISP1161A1BD Universal Serial Bus single-chip host and device controller
ISP1161A1BM Universal Serial Bus single-chip host and device controller
ISP1161BD Full-speed Universal Serial Bus single-chip host and device controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1161ABM,518 功能描述:USB 接口集成電路 DO NOT USE ORDER ISP1161A1BM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161ABM,551 功能描述:USB 接口集成電路 DO NOT USE ORDER ISP1161A1BM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161ABM,557 功能描述:USB 接口集成電路 DO NOT USE ORDER ISP1161A1BM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161ABM-S 功能描述:IC USB HOST CTRL FULL-SPD 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1161ABM-T 功能描述:IC USB HOST CTRL FULL-SPD 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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