參數(shù)資料
型號: ISP1161ABM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 65/134頁
文件大?。?/td> 587K
代理商: ISP1161ABM
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
65 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.4 HC DMA and interrupt control registers
10.4.1
HcHardwareConfiguration register (R/W: 20H/A0H)
1. Bit 0, InterruptPinEnable, is used as pin INT1’s master interrupt enable. This bit
should be used together with the register Hc
μ
PInterruptEnable to enable pin
INT1.
2. Bits 4 and 3 are fixed at logic 0 and logic 1 for the ISP1161A.
Code (Hex): 20 —
read
Code (Hex): A0 —
write
Table 36:
Bit
Symbol
HcHardwareConfiguration register: bit allocation
15
14
reserved
13
12
11
10
9
8
2_Down
streamPort
15K
resistorsel
0
R/W
4
DataBusWidth[1:0]
Suspend
ClkNotStop
AnalogOC
Enable
reserved
DACKMode
Reset
Access
Bit
Symbol
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
R/W
0
EOTInput
Polarity
0
R/W
DACKInput
Polarity
0
R/W
DREQOut
putPolarity
1
R/W
InterruptOut
putPolarity
0
R/W
InterruptPi
nTrigger
0
R/W
InterruptPin
Enable
0
R/W
Reset
Access
0
1
R/W
R/W
Table 37:
Bit
15 to 13 -
12
HcHardwareConfiguration register: bit description
Symbol
Description
reserved
0 —
use external 15 k
resistors for downstream
ports.
Power-up value
2_DownstreamPort15Kresistor
Sel
1 —
built-in resistors for downstream ports
0 —
clock can be stopped
11
SuspendClkNotStop
1 —
clock can not be stopped
0 —
use external OC detection. Digital input
10
AnalogOCEnable
1 —
use on-chip OC detection. Analog input
reserved
0 —
normal operation. DACK1 is used with read
and write signals. Power-up value
9
8
-
DACKMode
1 —
reserved
0 —
active LOW. Power-up value
7
EOTInputPolarity
1 —
active HIGH
0 —
active LOW. Power-up value
6
DACKInputPolarity
1 —
reserved
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