參數(shù)資料
型號: ISP1161ABM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 121/134頁
文件大?。?/td> 587K
代理商: ISP1161ABM
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
121 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
18.2.6
DC single-cycle DMA read timing in DACK-only mode
18.2.7
DC single-cycle DMA write timing in DACK-only mode
Table 122: Dynamic characteristics: DC single-cycle DMA read timing in DACK-only mode
Symbol
Parameter
t
ASRP
DREQ off after DACK on
t
ASAP
DACK pulse width
t
ASAP
+ t
APRS
DREQ on after DACK off
t
ASDV
data valid after DACK on
t
APDZ
data hold after DACK off
Conditions
Min
-
25
180
-
-
Typ
-
-
-
-
-
Max
40
-
-
22
3
Unit
ns
ns
ns
ns
ns
(1) Programmable polarity: shown as active LOW.
Fig 57. DC single-cycle DMA read timing in DACK-only mode.
004aaa112
DACK2
(1)
DREQ2
tASRP
tAPRS
tASDV
tAPDZ
DATA
tASAP
Table 123: Dynamic characteristics: DC single-cycle DMA write timing in DACK-only mode
Symbol
Parameter
t
ASRP
DREQ2 off after DACK2 on
t
ASAP
+ t
APRS
DREQ2 on after DACK2 off
t
DVAP
data setup before DACK2 off
t
APDZ
data hold after DACK2 off
Conditions
Min
-
180
5
3
Typ
-
-
-
-
Max
40
-
-
-
Unit
ns
ns
ns
ns
(1) Programmable polarity: shown as active LOW.
Fig 58. DC single-cycle DMA write timing in DACK-only mode.
004aaa113
DACK2
(1)
DREQ2
tASRP
tAPRS
tASDV
tAPDZ
DATA
tASAP
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