參數(shù)資料
型號: ISP1161ABM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 9/134頁
文件大?。?/td> 587K
代理商: ISP1161ABM
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
9 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
DACK2
28
I
DC DMA acknowledge input; when not in use, this pin must
be connected to V
CC
via an external 10 k
resistor
HC interrupt output; programmable level, edge triggered
and polarity; see
Section 10.4.1
DC interrupt output; programmable level, edge triggered
and polarity; see
Section 13.1.4
test output; used for test purposes only; this pin is not
connected during normal operation
reset input (Schmitt trigger); a LOW level produces an
asynchronous reset (internal pull-up resistor)
indicates to the HC software the Number of Downstream
Ports (NDP) present:
INT1
29
O
INT2
30
O
TEST
31
O
RESET
32
I
NDP_SEL
33
I
0 —
select 1 downstream port
1 —
select 2 downstream ports
only changes the value of the NDP field in the
HcRhDescriptorA register; both ports will always be
enabled; see
Section 10.3.1
(internal pull-up resistor)
DMA master device to inform the ISP1161A of end of DMA
transfer; active level is programmable; see
Section 10.4.1
digital ground
DC ‘suspend’ state indicator output; active HIGH
DC wake-up input; generates a remote wake-up from
‘suspend’ state (active HIGH); when not in use, this pin
must be connected to DGND via an external 10 k
resistor
(internal pull-down resistor)
GoodLink LED indicator output (open-drain, 8 mA); the
LED is default ON, blinks OFF upon USB traffic; to connect
a LED use a series resistor of 470
(V
CC
= 5.0 V) or
330
(V
CC
= 3.3 V)
DC USB upstream port V
BUS
sensing input; when not in
use, this pin must be connected to DGND via a 1 M
resistor
HC wake-up input; generates a remote wake-up from
‘suspend’ state (active HIGH); when not in use, this pin
must be connected to DGND via an external 10 k
resistor
(internal pull-down resistor)
programmable clock output (3 MHz to 48 MHz); default
12 MHz
HC ‘suspend’ state indicator output; active HIGH
crystal input; connected directly to a 6 MHz crystal; when
XTAL1 is connected to an external clock source, pin XTAL2
must be left open
crystal output; connected directly to a 6 MHz crystal; when
pin XTAL1 is connected to an external clock source, this
pin must be left open
EOT
34
I
DGND
D_SUSPEND
D_WAKEUP
35
36
37
-
O
I
GL
38
O
D_VBUS
39
I
H_WAKEUP
40
I
CLKOUT
41
O
H_SUSPEND
XTAL1
42
43
O
I
XTAL2
44
O
Table 2:
Symbol
[1]
Pin description for LQFP64
…continued
Pin
Type
Description
相關PDF資料
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ISP1161 Full-speed Universal Serial Bus single-chip host and device controller
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