參數(shù)資料
型號(hào): HYB18L256160B
廠商: QIMONDA
英文描述: DRAMs for Mobile Applications 256-Mbit Mobile-RAM
中文描述: DRAM的針對(duì)移動(dòng)應(yīng)用256兆移動(dòng)RAM
文件頁(yè)數(shù): 45/58頁(yè)
文件大?。?/td> 1766K
代理商: HYB18L256160B
Data Sheet
Rev. 1.73, 2006-09
01302004-CZ2R-J9SE
45
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
TABLE 17
Current state definitions
TABLE 18
State Definitions 2
TABLE 19
State Defintions 3
9) READs or WRITEs listed in the Command/Action column include READs or WRITEs with Auto Precharge enabled and READs or WRITEs
with Auto Precharge disabled.
10) May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
11) Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
Idle
Row Active
The bank has been precharged, and
t
RP
has been met
A row in the bank has been activated, and
t
RCD
has been met. No data bursts/accesses and no
register accesses are in progress
A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or
been terminated
A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or
been terminated
Read
Write
Precharging
Starts with registration of a PRECHARGE command and ends when
t
RP
is met. Once
t
RP
is met,
the bank is in the “idle” state
Starts with registration of an ACTIVE command and ends when
t
RCD
is met. Once
t
RCD
is met,
the bank is in the “row active” state
Starts with registration of a READ command with Auto Precharge enabled and ends when
t
RP
has been met. Once
t
RP
is met, the bank is in the idle state
Starts with registration of a WRITE command with Auto Precharge enabled and ends when
t
RP
has been met. Once
t
RP
is met, the bank is in the idle state
Row Activating
Read with AP
Enabled
Write with AP
Enabled
Refreshing
Starts with registration of an AUTO REFRESH command and ends when
t
RC
is met. Once
t
RC
is
met, the SDRAM is in the “all banks idle” state
Starts with registration of a MODE REGISTER SET command and ends when
t
MRD
has been
met. Once
t
MRD
is met, the SDRAM is in the “all banks idle” state
Starts with registration of a PRECHARGE ALL command and ends when
t
RP
is met. Once
t
RP
is
met, all banks are in the idle state
Accessing MR
Precharging All
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