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參數(shù)資料
| 型號： | HYB18L256160B |
| 廠商： | QIMONDA |
| 英文描述： | DRAMs for Mobile Applications 256-Mbit Mobile-RAM |
| 中文描述： | DRAM的針對移動應(yīng)用256兆移動RAM |
| 文件頁數(shù)： | 12/58頁 |
| 文件大?。?/td> | 1766K |
| 代理商： | HYB18L256160B |
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Data Sheet
Rev. 1.73, 2006-09
01302004-CZ2R-J9SE
12
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
2.2.1.6
Partial Array Self Refresh (PASR)
Partial Array Self Refresh is a power-saving feature specific to Mobile RAMs. With PASR, self refresh may be restricted to
variable portions of the total array. The selection comprises all four banks (default), two banks, one bank, half of one bank, and
a quarter of one bank. Data written to the non activated memory sections will get lost after a period defined by
t
REF
(cf.
Table 15
).
2.2.1.7
Temperature Compensated Self Refresh (TCSR)
DRAM devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain the stored
information. This refresh requirement heavily depends on the die temperature: high temperatures correspond to short refresh
periods, and low temperatures correspond to long refresh periods.
The Mobile-RAM is equipped with an on-chip temperature sensor which continuously senses the actual die temperature and
adjusts the refresh period in Self Refresh mode accordingly. This makes any programming of the TCSR bits in the Extended
Mode Register obsolete. It also is the superior solution in terms of compatibility and power-saving, because
it is fully compatible to all processors that do not support the Extended Mode Register
it is fully compatible to all applications that only write a default (worst case) TCSR value, e.g. because of the lack of an
external temperature sensor
it does not require any processor interaction for regular TCSR updates
2.2.1.8
Selectable Drive Strength
The drive strength of the DQ output buffers is selectable via bits A5 and A6 and shall be set load dependent. The half drive
strength is suitable for typical Mobile-RAM applications. The full drive strength is intended for heavier loaded systems.
I
-
V
curves for full drive strength and half drive strength can be found in
Table 29
.
TCSR
[4:3]
w
Temperature Compensated Self Refresh
XX
B
Superseded by on-chip temperature sensor (see text)
Partial Array Self Refresh
000
B
all banks (default)
001
B
1/2 array (BA1 = 0)
010
B
1/4 array (BA1 = BA0 = 0)
101
B
1/8 array (BA1 = BA0 = RA12 = 0)
110
B
1/16 array (BA1 = BA0 = RA12 = RA11 = 0)
Note: All other bit combinations are RESERVED.
PASR
[2:0]
w
Field
Bits
Type
Description
相關(guān)PDF資料 |
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| HYMP112S64LMP8-C4 | DDR2 SDRAM SO-DIMM |
| HYMP112S64LMP8-C5 | DDR2 SDRAM SO-DIMM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18L256160BC-7.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:BJAWBMSpecialty DRAMs Mobile-RAM |
| HYB18L256160BC-75 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DRAMs for Mobile Applications |
| HYB18L256160BCL-7.5 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:DRAMs for Mobile Applications 256-Mbit Mobile-RAM |
| HYB18L256160BCX-7.5 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:DRAMs for Mobile Applications 256-Mbit Mobile-RAM |
| HYB18L256160BF | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DRAMs for Mobile Applications |
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