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參數(shù)資料
| 型號： | HY27SA081G1M-VPEB |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | PROM |
| 英文描述： | 128M X 8 FLASH 1.8V PROM, 12000 ns, PDSO48 |
| 封裝： | 12 X 17 MM, 0.70 MM HEIGHT, LEAD FREE, WSOP1-48 |
| 文件頁數(shù)： | 2/45頁 |
| 文件大?。?/td> | 675K |
| 代理商： | HY27SA081G1M-VPEB |
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Rev 0.3 / May. 2004
10
Preliminary
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Data Output
Data Output bus operations are used to read: the data in the memory array, the Status Register, the Electronic Signa-
ture and the Serial Number. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is
Low, and Command Latch Enable is Low. The data is output sequentially using the Read Enable signal.
See Figure 24 and Table 15 for details of the timings requirements.
Write Protect
Write Protect bus operations are used to protect the memory against program or erase operations. When the Write
Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array
cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up.
Standby
When Chip Enable is High the memory enters Standby mode, the device is deselected, outputs are disabled and power
consumption is reduced.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY27UA081G1M-TIB | 128M X 8 FLASH 3.3V PROM, 12000 ns, PDSO48 |
| HY27US08121B-TPIS | 64M X 8 FLASH 3.3V PROM, 18 ns, PDSO48 |
| HY27US08121B-FIB | 64M X 8 FLASH 3.3V PROM, 18 ns, PBGA63 |
| HY27US081G1MSES | 128M X 8 FLASH 2.7V PROM, 45 ns, PDSO48 |
| HY27US081G1MTCS | 128M X 8 FLASH 2.7V PROM, 45 ns, PDSO48 |
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