參數(shù)資料
型號(hào)： HMP8117CNZ
廠商： Intersil
文件頁(yè)數(shù)： 6/45頁(yè)
文件大?。?/td> 0K
描述： IC VIDEO DECODER NTSC/PAL 80PQFP
標(biāo)準(zhǔn)包裝： 66
類型： 視頻解碼器
應(yīng)用： 視頻
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 80-BQFP
供應(yīng)商設(shè)備封裝： 80-QFP（14x20）
包裝： 托盤
14
FN4643.4
July 29, 2009
8-Bit BT.656 Output
For the BT.656 output mode, data is output following each
rising edge of CLK2. The BT.656 EAV and SAV formats are
shown in Table 5 and the pixel output timing is shown in
Figure 14. The EAV and SAV timing is determined by the
programmed horizontal and vertical blank timing.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2.
During the blanking intervals, the YCbCr outputs have a
value of 16 for Y and 128 for Cb and Cr, unless ancillary data
is present.
NOTES:
12. Y0 is the first active luminance pixel of a line. Cb0 and Cr0 are first active chrominance pixels in a line. Cb and Cr will alternate every cycle due
to the 4:2:2 subsampling.
13. BLANK is asserted per Figure 7.
14. DVALID is asserted for every valid pixel during both active and blanking regions.
FIGURE 12. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 1)
Y0
Cb0
Y1
Cr0
Y2
Cb2
Y3
Cr2
Y4
Cb4
CLK
DVALID
P15-P8
P7-P0
tDVLD
NOTES:
15. BLANK is asserted per Figure 7.
16. DAVLID is asserted for every valid pixel during both active and blanking regions. DVALID is not a 50% duty cycle synchronous output and will
appear to jitter as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs.
FIGURE 13. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 1)
R0
G0
R1
G0
R2
G2
R3
G2
R4
G4
CLK
DVALID
BLANK
tDVLD
B0
B1
B2
B3
B4
P15-P11
P10-P5
P4-P0
[P9-P5]
[P14-P10]
HMP8117
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