參數(shù)資料
型號(hào)： HMP8117CNZ
廠商： Intersil
文件頁(yè)數(shù)： 4/45頁(yè)
文件大?。?/td> 0K
描述： IC VIDEO DECODER NTSC/PAL 80PQFP
標(biāo)準(zhǔn)包裝： 66
類(lèi)型： 視頻解碼器
應(yīng)用： 視頻
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 80-BQFP
供應(yīng)商設(shè)備封裝： 80-QFP（14x20）
包裝： 托盤(pán)
12
FN4643.4
July 29, 2009
Pixel Output Port
Pixel data is output via the P0-P15 pins. Refer to Table 4 for
the output pin definition as a function of the output mode.
Refer to the section “CYCLE SLIPPING AND REAL-TIME
PIXEL JITTER” for PLL and interface considerations.
8-Bit YCbCr Output
Each YCbCr data byte is output following each rising edge of
CLK2. The YCbCr data is multiplexed as [Cb Y Cr Y
′ Cb Y
Cr Y
′...], with the first active data each scan line containing
Cb data. The pixel output timing is shown in Figures 8 and 9.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2. When BLANK
is asserted and VBIVALID is deasserted, the YCbCr outputs
have a value of 16 for Y and 128 for Cb and Cr. The behavior
of the DVALID output is determined by bit 4 (DVLD_LTC) of
the GENLOCK CONTROL register 04H.
16-Bit YCbCr, 15-Bit RGB, or 16-RGB Output
For 16-bit YCbCr, 15-bit RGB data, or 16-bit RGB output
modes, the data is output following the rising edge of CLK2
with DVALID asserted. Either linear or gamma-corrected
RGB data may be output. The pixel output timing is shown in
Figures 10 to 13.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2. When BLANK
is asserted and VBIVALID is deasserted, the YCbCr outputs
have a value of 16 for Y and 128 for Cb and Cr; the RGB
outputs have a value of 0.
The behavior of the DVALID output is determined by bit 4
(DVLD_LTC) and bit 5 (DLVD_DCYC) of the GENLOCK
CONTROL register 04H.
NOTE:
6. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate every
cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values are forced to blanking levels.
FIGURE 8. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 0)
CLK
DVALID
P[15-8]
tDVLD
Cb0
Y0
Cr0
Cb2
Y2
Cr2
Y1
Y3
Cb4
Y4
BLANK
CLK
DVALID
P[15-8]
tDVLD
Cb0
Y0
Cr0
Cb2
Y2
Cr2
Y1
Y3
Cb4
NOTES:
7. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate every
cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values are forced to blanking levels.
8. When DVLD_LTC is set to 1, the polarity of DVALID needs to be set to active low, otherwise DVALID will stay low during active video and be
gated with the clock only during the blanking interval.
FIGURE 9. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 1)
Y4
BLANK
HMP8117
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