SUB ADDRESS = 35H BIT NO. FUNCTION DESCRIPTION" />
參數(shù)資料
型號： HMP8117CNZ
廠商： Intersil
文件頁數(shù)： 30/45頁
文件大小： 0K
描述： IC VIDEO DECODER NTSC/PAL 80PQFP
標(biāo)準(zhǔn)包裝： 66
類型： 視頻解碼器
應(yīng)用： 視頻
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 80-BQFP
供應(yīng)商設(shè)備封裝： 80-QFP（14x20）
包裝： 托盤
36
FN4643.4
July 29, 2009
TABLE 57. END V_BLANK REGISTER
SUB ADDRESS = 35H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Negate BLANK
Output Signal
This 8-bit register specifies the line number to negate BLANK each field.
For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even fields. For
PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even fields.
12H
TABLE 58. END HSYNC REGISTER
SUB ADDRESS = 36H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Negate HSYNC
Output Signal
This 8-bit register specifies the horizontal count at which to negate HSYNC each scan line.
Values may range from 0 (0000 0000) to 510 (1111 1111) CLK2 cycles. The leading edge of
HSYNC is count 00H.
30H
TABLE 59. HSYNC DETECT WINDOW REGISTER
SUB ADDRESS = 37H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Horizontal Sync
Detect Window
This 8-bit register specifies the width of the timing window (in 1x clock samples) for the digital
PLL to accept horizontal sync pulses in each line. The window is centered about where the
horizontal sync pulse should be located.
If the horizontal sync pulse falls inside the window, the digital PLL maintains normal lock timing.
If the horizontal sync pulse falls outside this window, the digital PLL will to enter the horizontal
lock acquisition mode based on the current setting for bits 3-2 of register 04H. Recommend
changing this register to 90H following reset in order to widen the window for poorly timed input
video sources.
20H
(Use 90H)
TABLE 60. MV CONTROL
SUB ADDRESS = 41H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
MV Stripe Detection
and Bypass Enable
Set to “1” to enable the detection and bypass of the MV Color Striping component. If this bit is
not enabled and the MV Color Striping component exists on the input signal, artifacts will be
clearly visible as horizontal streaks in the output data. This bit must be enabled for the MV
Detection Status of register 0EH to be updated.
0B
6
MV PSP Detection
Enable
Set to “1” to enable detection of the MV Pseudo Sync Pulse (PSP)
component. If the MV PSP component exists on the input signal, this bit must be enabled for the
MV Detection Status of register 0EH to be updated.
0B
5-3
MV PSP Detection
Count
Defines the number of extra sync pulses required before declaring the Pseudo Sync Pulse (PSP)
component in the MV Detection Status of register 0EH. The PSP component must also be
present for the number of fields defined in bits 2-0 below.
100B
2-0
MV Detection
Field Count
Defines the minimum number of fields that an MV component must be present for in order to
change the MV Detection Status of register 0EH. Add 2 to bits 2-0 to obtain the minimum field
count. Ex: The default of 110B is actually 6 + 2 = 8 fields.
110B
TABLE 61. RESERVED
SUB ADDRESS = 42H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Reserved
Set bits 5-4 to 11B for optimum performance.
00H
(Use 30H)
HMP8117
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