參數(shù)資料
型號(hào)： HMP8117CNZ
廠商： Intersil
文件頁(yè)數(shù)： 33/45頁(yè)
文件大?。?/td> 0K
描述： IC VIDEO DECODER NTSC/PAL 80PQFP
標(biāo)準(zhǔn)包裝： 66
類(lèi)型： 視頻解碼器
應(yīng)用： 視頻
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 80-BQFP
供應(yīng)商設(shè)備封裝： 80-QFP（14x20）
包裝： 托盤(pán)
39
FN4643.4
July 29, 2009
LCAP
76
I
0.1F
to AGND
Storage capacitor for Luminance signal DC restoration. The LCAP voltage offsets the sync
tip to the lower reference of the A/D. A 0.1
μF capacitor should be connected between this
pin and AGND. This capacitor should be as close to this pin as possible for best
performance.
CCAP
29
I
0.1F
to AGND
Storage capacitor for Chrominance signal DC restoration. The CCAP voltage offsets the
chroma signal to mid-range of the A/D. A 0.1
μF capacitor should be connected between
this pin and AGND. This capacitor should be as close to this pin as possible for best
performance.
P0-P15
42, 43, 45,
47-51, 54-58,
60, 63, 64
ON/A
Pixel output pins. See Table 3. These pins are three-stated after a RESET or software reset.
HSYNC
71
O
10k
Ω Pullup
Horizontal sync output. HSYNC is asserted during the horizontal sync intervals. The
polarity of HSYNC is programmable. This pin is three-stated after a RESET or software
reset and should be pulled high through a 10k
Ω resistor.
VSYNC
70
O
10k
Ω Pullup
Vertical sync output. VSYNC is asserted during the vertical sync intervals. The polarity of
VSYNC is programmable. This pin is three-stated after a RESET or software reset and
should be pulled high through a 10k
Ω resistor.
FIELD
67
O
10k
Ω Pullup
FIELD output. The polarity of FIELD is programmable. This pin is three-stated after a
RESET or software reset and should be pulled high through a 10k
Ω resistor.
DVALID
66
O
10k
Ω Pullup
Data valid output. DVALID is asserted during CLK2 cycles that contain valid pixel data. This
pin is three-stated after a RESET or software reset and should be pulled high through a
10k
Ω resistor.
BLANK
65
O
10k
Ω Pullup
Composite blanking output. BLANK is asserted during the horizontal and vertical blanking
intervals. The polarity of BLANK is programmable. This pin is three-stated after a RESET
or software reset and should be pulled high through a 10k
Ω resistor.
VBIVALID
61
O
10k
Ω Pullup
Vertical Blanking Interval Valid output. VBIVALID is asserted during CLK2 cycles that
contain valid VBI (Vertical Blanking Interval) data such as Closed Captioning, Teletext, and
WSS data. The polarity of VBIVALID is programmable. This pin is three-stated after a
RESET or software reset and should be pulled high through a 10k resistor.
INTREQ
44
O
10k
Ω Pullup
Interrupt Request Output. This is an open-drain output and requires an external 10k
Ω pull-
up resistor to VCC.
CLK2
38
I
2x pixel clock input. This clock must be a continuous, free-running clock. Refer to Table 1
for allowable CLK2 frequencies for each video standard and aspect ratio. For best
performance, use termination resistor(s) to minimize pulse overshoot and reflections.
RESET
34
I
Reset control input. A logical zero for a minimum of four CLK2 cycles resets the device.
RESET must be a logical one for normal operation.
SA
27
I
10k
Ω Pullup
or
0
Ω Pulldown
I2C slave address select input. This was formerly the WPE pin on HMP8112/15 decoders.
If the SA pin is pulled low, the I2C address is 1000100xB or 88H. If the SA pin is pulled high,
the address is 1000101xB or 8AH. (The ‘x’ bit is the address is the I2C read flag.)
SDA
40
I/O
4k
Ω Pullup
I2C data input/output. This pin should be pulled high through a 4k
Ω resistor.
SCL
41
I
4k
Ω Pullup
I2C clock input. This pin should be pulled high through a 4k
Ω resistor.
VAA
2, 12, 14
I
0.1F
to AGND
Analog power supply pins. All VAA pins must be connected together.
AGND
1, 3, 10, 11,
15,16, 21, 22,
23, 24
I
none
Analog ground pins. All AGND pins must be connected together. Refer to Applications
section for recommended grounding scheme.
VCC
26, 31,37, 52,
59, 68, 75, 79
I
Digital power supply pins. All VCC pins must be connected together.
GND
25, 33, 35, 36,
39, 46, 53, 62,
69, 72, 80
I
Digital ground pins. All GND pins must be connected together.
NC
4, 13, 18,
20, 30, 32,
73, 74, 77
No Connect pins. These pins may be left floating or tied to GND.
Pin Descriptions (Continued)
PIN
NAME
PIN
NUMBER
I/O
PASSIVE
DESCRIPTION
HMP8117
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