SUB ADDRESS = 1DH BIT NO. FUNCTION DESCR" />
參數(shù)資料
型號： HMP8117CNZ
廠商： Intersil
文件頁數(shù)： 26/45頁
文件大?。?/td> 0K
描述： IC VIDEO DECODER NTSC/PAL 80PQFP
標準包裝： 66
類型： 視頻解碼器
應(yīng)用： 視頻
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 80-BQFP
供應(yīng)商設(shè)備封裝： 80-QFP（14x20）
包裝： 托盤
32
FN4643.4
July 29, 2009
TABLE 38. VIDEO GAIN ADJUST REGISTER
SUB ADDRESS = 1DH
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Video Gain Adjust
This register is enabled by the selection of “fixed gain control” mode in the Analog Input Control
register 05H bits 7-4. The value of this register selects a combined analog attenuation and a
digital gain factor which is applied to both Luma and Chroma input channels. The gain factor is
selected from nonlinear lookup table and may range in value from 0.5x (CEH) to 1.99x (33H).
Refer to Table 39 below. The Register Values in italics below mark the approximate analog
attenuation ladder switching points.
80H
TABLE 39. VIDEO GAIN REGISTER LOOKUP TABLE
Video
Gain
Reg.
Value
Video
Gain
Reg.
Value
Video
Gain
Reg.
Value
Video
Gain
Reg.
Value
Video
Gain
Reg.
Value
Video
Gain
Reg.
Value
0.50
0.51
0.52
0.53
0.54
0.55
206/CEH
202/CAH
197/C5H
193/C1H
191/BFH
187/BBH
0.67
0.68
0.69
0.70
0.71
0.72
153/99H
151/97H
150/96H
147/93H
145/91H
143/8FH
0.84
0.85
0.86
0.87
0.88
0.89
123/7BH
121/79H
119/77H
118/76H
117/75H
115/73H
1.03
1.04
1.05
1.06
1.07
1.08
100/64H
99/63H
98/62H
97/61H
96/60H
95/5FH
1.23
1.25
1.27
1.28
1.30
1.31
83/53H
82/52H
81/51H
80/50H
79/4FH
78/4EH
1.55
1.57
1.59
1.63
1.65
1.67
66/42H
65/41H
64/40H
63/3FH
62/3EH
61/3DH
0.56
0.57
0.58
0.59
0.60
0.61
183/B7H
180/B4H
178/B2H
174/AEH
171/ABH
169/A9H
0.73
0.74
0.75
0.76
0.77
0.78
141/8DH
139/8BH
137/89H
136/88H
134/86H
132/84H
0.90
0.91
0.92
0.94
0.95
0.96
114/72H
113/71H
111/6FH
110/6EH
109/6DH
107/6BH
1.09
1.10
1.12
1.13
1.14
1.15
94/5EH
93/5DH
92/5CH
91/5BH
90/5AH
89/59H
1.33
1.34
1.37
1.38
1.40
1.42
77/4DH
76/4CH
75/4BH
74/4AH
73/49H
72/48H
1.70
1.73
1.76
1.79
1.82
1.86
60/3CH
59/3BH
58/3AH
57/39H
56/38H
55/37H
0.62
0.63
0.64
0.65
0.66
167/A7H
164/A4H
161/A1H
159/9FH
156/9CH
0.79
0.80
0.81
0.82
0.83
130/82H
128/80H
126/7EH
125/7DH
124/7CH
0.97
0.98
1.00
1.01
1.02
106/6AH
104/68H
103/67H
102/66H
101/65H
1.16
1.18
1.20
1.21
1.22
88/58H
87/57H
86/56H
85/55H
84/54H
1.44
1.46
1.48
1.51
1.52
71/47H
70/46H
69/45H
68/44H
67/43H
1.89
1.93
1.97
1.99
54/36H
53/35H
52/34H
51/33H
TABLE 40. SHARPNESS ADJUST REGISTER
SUB ADDRESS = 1EH
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Reserved
00B
5-0
Sharpness
Adjust
Specifies the amount of high frequency gain control for luminance signals (either 2.6MHz or
FSC), as determined by the Luma Processing register 08H. The gain ranges from +12dB (11
1111B) to -12dB (00 0100B). A value of 0dB (“01 0000”) has no effect on the data.
010000B
HMP8117
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