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參數(shù)資料
| 型號： | HMP8117CNZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 13/45頁 |
| 文件大小： | 0K |
| 描述： | IC VIDEO DECODER NTSC/PAL 80PQFP |
| 標準包裝： | 66 |
| 類型： | 視頻解碼器 |
| 應用： | 視頻 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-BQFP |
| 供應商設備封裝： | 80-QFP（14x20） |
| 包裝： | 托盤 |
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20
FN4643.4
July 29, 2009
During PAL (B, D, G, H, I, N, NC) operation, the first possible
line of VBI data are lines 6 and 318, and the last possible
lines are the last blanked scan lines. Lines 623-5 and 311-
317 are always blanked.
During PAL (M) operation, the first possible line of VBI data
is lines 7 and 269, and the last possible lines are the last
blanked scan lines. Lines 523-6 and 261-268 are always
blanked.
Real Time Control Interface
The Real Time Control Interface (RTCI) outputs timing
information for a NTSC/PAL encoder as BT.656 ancillary
data. This allows the encoder to generate “clean” output
video.
RTCI information via BT.656 ancillary data is shown in Table
9. If enabled, this transfer occurs once per line and is
completed before the start of the SAV sequence.
The PSW bit is always a “0” for NTSC encoding. During PAL
encoding, it indicates the sign of V (“0” = negative;
“1” = positive) for that scan line.
Host Interface
All internal registers may be written to or read by the host
processor at any time, except for those bits identified as
read-only. The bit descriptions for the control registers are
listed beginning with Table 10.
The HMP8117 supports the fast-mode (up to 400kbps) I2C
interface consisting of the SDA and SCL pins. The device
acts as a slave for receiving and transmitting data over the
serial interface. When the interface is not active, SCL and
SDA must be pulled high using external 4k
Ω pull-up
resistors. The SA input pin determines the slave address for
the HMP8117. If the SA pin is pulled low, the address is
1000100xB. If the SA pin is pulled high through a 10kΩ pull-
up resistor, the address is 1000101xB. (This ‘x’ bit in the
address is the I2C read flag.)
Data is placed on the SDA line when the SCL line is low and
held stable when the SCL line is pulled high. Changing the
state of the SDA line while SCL is high will be interpreted as
either an I2C bus START or STOP condition as indicated by
Figure 18.
During I2C write cycles, the first data byte after the slave
address is treated as the control register sub address and is
written into the internal address register. Any remaining data
bytes sent during an I2C write cycle are written to the control
registers, beginning with the register specified by the
address register as given in the first byte. The address
register is then auto-incremented after each additional data
byte sent on the I2C bus during a write cycle. Writes to
reserved bits within registers or reserved registers are
ignored.
TABLE 9. OUTPUTTING RTCI AS BT.656 ANCILLARY DATA
PIXEL INPUT
P15
P14
P13
P12
P11
P10
P9
P8
Preamble
0
000000
1
111111
1
111111
Data ID
P14
ep
110101
Data Block Number
P14
ep
000001
Data Word Count
P14
ep
000011
HPLL
Increment
P14
ep
000000
P14
ep
000000
P14
ep
000000
P14
ep
000000
FSCPLL
Increment
P14
ep
PSW
0
bit 31
bit 30
bit 29
bit 28
P14
ep
F2 = 0
F1 = 0
bit 27
bit 26
bit 25
bit 24
:
P14
ep
0
bit 7
bit 6
bit 5
bit 4
P14
ep
0
bit 3
bit 2
bit 1
bit 0
CRC
P14
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
NOTES:
39. ep = even parity for P8-P13.
40. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored.
HMP8117
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