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參數(shù)資料
| 型號： | HMP8117CNZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 45/45頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DECODER NTSC/PAL 80PQFP |
| 標準包裝： | 66 |
| 類型： | 視頻解碼器 |
| 應用： | 視頻 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-BQFP |
| 供應商設備封裝： | 80-QFP（14x20） |
| 包裝： | 托盤 |
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9
FN4643.4
July 29, 2009
for gamma = 2.2:
for R
′B′ < 0.0812*31, G′ < 0.0812*63
R = (31)((R
′/31)/4.5)
G = (63)((G
′/63)/4.5)
B = (31)((B
′/31)/4.5)
for R
′B′ >= 0.0812*31, G′ >= 0.0812*63
R = (31)(((R
′/31) + 0.099)/1.099)2.2
G = (63)(((G
′/63) + 0.099)/1.099)2.2
B = (31)(((B
′/31) + 0.099)/1.099)2.2
for gamma = 2.8:
R = (31)(R
′/31)2.8
G = (63)(G
′/63)2.8
B = (31)(B
′/31)2.8
Built-in Video Generation
The decoder can be configured to output a full-screen of built-in
blue, black or 75% color bar patterns. The type of pattern
generated is determined by bits 2-1 of the OUTPUT FORMAT
register 02H. When built-in video generation is not desired, the
bits need to be set for normal operation to pass decoded video.
If the decoder is currently locked to a video source on the
input, the output data timing will be based on the input video
source. If an input video source is not detected, internally-
generated output data timing will be used. The following
table lists the data codes output for each built-in video
pattern in YCbCr format.
Pixel Port Timing
The the timing and format of the output data and control
signals is presented in the following sections. Refer to the
section “CYCLE SLIPPING AND REAL-TIME PIXEL
JITTER” for PLL and interface considerations.
HSYNC and VSYNC Timing
The HSYNC and VSYNC output timing is VMI v1.4 compatible.
Figures 3-6 illustrate the video timing. The leading edge of
HSYNC is synchronous to the video input signal and has a
fixed latency due to internal pipeline processing. The pulse
width of the HSYNC is defined by the END HSYNC register
36H, where the trailing edge of HSYNC has a programmable
delay of 0-510 CLK2 cycles from the leading edge.
The leading edge of VSYNC is asserted approximately half way
through the first serration pulse of each field. An accumulator is
used to detect a low-time period within the serration pulse.
Since the leading edge of VSYNC is detected, it should not be
used for timing with respect to HSYNC or BLANK.
The trailing edge of VSYNC implements the VMI handshake
with HSYNC in order to determine field information without
using the FIELD pin. For an odd field, the trailing edge of
VSYNC is 5 ±1 CLK2 cycles after the trailing edge of the
HSYNC that follows the last equalization pulse. Refer to
is 5 ±1 CLK2 cycles after the leading edge of the HSYNC that
Field Timing
When field information can be determined from the input
video source, the FIELD output pin reflects the video source
field state. When field information cannot be determined
from the input video source, the FIELD output pin alternates
its state at the beginning of each field. FIELD changes state
5±1 CLK2 cycles before the leading edge of VSYNC.
TABLE 2. BUILT-IN VIDEO PATTERN DATA CODES
PATTERN: COLOR
Y
Cb
Cr
75% Color Bar: White
Yellow
Cyan
Green
Magenta
Red
Blue
Black
B4H
A2H
83H
70H
54H
41H
23H
10H
80H
2CH
9CH
48H
B8H
64H
D4H
80H
8EH
2CH
3AH
C6H
D4H
72H
80H
Blue Screen: Blue
4BH
D9H
88H
Black Screen: Black
10H
80H
VIDEO
VSYNC
FIELD
‘EVEN’ FIELD
FIGURE 3. NTSC(M) AND PAL(M) ODD FIELD TIMING
‘ODD’ FIELD
HSYNC
INPUT
523
524
525
1234567
522
521
12345678910
525
524
PAL(M) LINE#
NTSC(M) LINE#
HMP8117
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