SUB ADDRESS = 03H BIT NUMBER FUNCTION DESCR" />
參數(shù)資料
型號： HMP8117CNZ
廠商： Intersil
文件頁數(shù)： 17/45頁
文件大?。?/td> 0K
描述： IC VIDEO DECODER NTSC/PAL 80PQFP
標準包裝： 66
類型： 視頻解碼器
應用： 視頻
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 80-BQFP
供應商設備封裝： 80-QFP（14x20）
包裝： 托盤
24
FN4643.4
July 29, 2009
TABLE 14. OUTPUT CONTROL REGISTER
SUB ADDRESS = 03H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7
Video Data
Output Enable
This bit is used to enable the P0-P15 outputs.
0 = Outputs 3-stated. 1 = Outputs enabled
0B
6
Video Timing
Output Enable
This bit is used to enable the HSYNC, VSYNC, BLANK, FIELD, VBIVALID, DVALID, and
INTREQ outputs. 0 = Outputs 3-stated. 1 = Outputs enabled
0B
5
FIELD Polarity
0 = Active low (low during odd fields). 1 = Active high (high during odd fields)
0B
4BLANK Polarity
0 = Active low (low during blanking). 1 = Active high (high during blanking)
0B
3
HSYNC Polarity
0 = Active low (low during horizontal sync). 1 = Active high (high during horizontal sync)
0B
2
VSYNC Polarity
0 = Active low (low during vertical sync). 1 = Active high (high during vertical sync)
0B
1DVALID Polarity
0 = Active low (low during valid pixel data). 1 = Active high (high during valid pixel data)
0B
0
VBIVALID Polarity
0 = Active low (low during VBI data). 1 = Active high (high during VBI data)
0B
TABLE 15. GENLOCK CONTROL REGISTER
SUB ADDRESS = 04H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Aspect Ratio
Mode
0 = Rectangular (BT.601) pixels
1 = Square pixels
0B
6
Freeze Output
Timing Enable
Setting this bit to a “1” freezes the output timing at the end of the field. Resetting this bit to a “0”
resumes normal operation at the start of the next field.
0 = Normal operation
1 = Freeze output timing
0B
5DVALID Duty Cycle
Control
(DVLD_DCYC)
This bit is ignored during the 8-bit YCbCr and BT.656 output modes.
During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
0 = DVALID has 50/50 duty cycle at the pixel output data rate
1 = DVALID goes active based on line-lock. This will cause DVALID to not have a 50/50 duty
cycle. This bit is intended to be used in maintaining backward compatibility with the HMP8112A
DVALID output timing.
0B
4DVALID Line Timing
Control
(DVLD_LTC)
During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
0 = DVALID present only during active video time on active scan lines
1 = DVALID present the entire scan line time on all scan lines
During the 8-bit YCbCr and BT.656 output modes, this bit defines the DVALID output as:
0 = Normal timing
1 = DVALID signal ANDed with CLK2
0B
3
Missing HSYNC
Detect Select
This bit specifies the number of missing horizontal sync pulses before entering horizontal lock
acquisition mode.
0 = 12 pulses
1 = 1 pulse
1B
2
Missing VSYNC
Detect Select
This bit specifies the number of missing vertical sync pulses before entering vertical lock
acquisition mode.
0 = 3 pulses
1 = 1 pulse
0B
1-0
CLK2 Frequency
This bit indicates the frequency of the CLK2 input clock.
00 = 24.54MHz10 = 29.5MHz
01 = 27.0MHz11 = Reserved
01B
HMP8117
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