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參數(shù)資料
| 型號： | HMP8117CNZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 29/45頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DECODER NTSC/PAL 80PQFP |
| 標準包裝： | 66 |
| 類型： | 視頻解碼器 |
| 應(yīng)用： | 視頻 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-BQFP |
| 供應(yīng)商設(shè)備封裝： | 80-QFP（14x20） |
| 包裝： | 托盤 |
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35
FN4643.4
July 29, 2009
TABLE 51. WSS_CRC_EVEN DATA REGISTER
SUB ADDRESS = 29H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Reserved
00B
5-0
Even Field
WSS CRC Data
If even field WSS is enabled and present during NTSC operation, this register is loaded with the
six bits of CRC information on line 283. It is always a “000000” during PAL operation. Data written
to this register is ignored.
000000B
TABLE 52. START H_BLANK LSB REGISTER
SUB ADDRESS = 30H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Assert BLANK
Output Signal
This 8-bit register is cascaded with Start H_BLANK High Register to form a 10-bit start horizontal
blank REGISTER. It specifies the horizontal count (in 1x clock cycles) at which to assert BLANK
each scan line. Bit 0 is always a “0”, so the start of horizontal blanking may only be done with two
pixel resolution. The leading edge of HSYNC is count 000H.
4AH
TABLE 53. START H_BLANK MSB REGISTER
SUB ADDRESS = 31H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
15-10
Reserved
000000B
9-8
Assert BLANK
Output Signal
This 2-bit register is cascaded with Start H_BLANK Low Register to form a 10-bit start horizontal
blank register. It specifies the horizontal count (in 1x clock cycles) at which to assert BLANK each
scan line. The leading edge of HSYNC is count 000H.
11B
TABLE 54. END H_BLANK REGISTER
SUB ADDRESS = 32H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Negate BLANK
Output Signal
This 8-bit register specifies the horizontal count (in 1x clock cycles) to negate BLANK each scan
line. For proper operation, bit 0 must always be set to “0”; therefore, the end of horizontal
blanking may only set with two pixel resolution. If bit 0 is set to “1”, the chroma/luma output data
may be swapped. The leading edge of HSYNC is count 000H.
7AH
TABLE 55. START V_BLANK LSB REGISTER
SUB ADDRESS = 33H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Assert BLANK
Output Signal
This 8-bit register is cascaded with Start V_BLANK High Register to form a 9-bit start vertical
blank register. It specifies the line number to assert BLANK each field.
For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even fields. For
PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even fields.
02H
TABLE 56. START V_BLANK MSB REGISTER
SUB ADDRESS = 34H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
15-9
Reserved
0000000B
8
Assert BLANK
Output Signal
This 1-bit register is cascaded with Start V_BLANK Low Register to form a 9-bit start vertical
blank register.
1B
HMP8117
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