參數(shù)資料
型號: HDMP-0452
英文描述: Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops
中文描述: 四端口旁路電路與光纖通道仲裁環(huán)路的CDR
文件頁數(shù): 9/12頁
文件大?。?/td> 273K
代理商: HDMP-0452
9
HP70841B
PATTERN
GENERATOR
HDMP-0452
HP83480A
DIGITAL
COMMUNICATION
ANALYZER
HP70311A
CLOCK SOURCE
CLOCK
+K28.5 –K28.5
REFCLK
TRIGGER
106.25 MHz
1062.5 MHz
DETERMINISTIC JITTER
± DATA
2
± FM_NODE[0]
BYPASS[0]–
BYPASS[1:4]–
± TO_NODE[0]
CH 1/2
2
1/10
1.4 V
BIAS TEE
N/C
106.25 MHz
1 k
1/2
53.125 MHz
HP70841B
PATTERN
GENERATOR
HDMP-0452
HP83480A
DIGITAL
COMMUNICATION
ANALYZER
HP70311A
CLOCK SOURCE
CLOCK
K28.7
REFCLK
TRIGGER
106.25 MHz
1062.5 MHz
RANDOM JITTER
± DATA
2
± FM_NODE[0]
BYPASS[0]–
BYPASS[1:4]–
± TO_NODE[0]
CH 1/2
2
1/10
1.4 V
BIAS TEE
N/C
106.25 MHz
1 k
Figure 7. Setup for measurement of deterministic jitter.
Figure 6. Setup for measurement of random jitter.
Figure 5. Eye diagram of FM_NODE[1]
±
high-speed differential output.
Note:
Measurement taken with a 2
7
-1 PRBS input to FM_NODE[0]
±
.
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