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參數(shù)資料
| 型號： | HDMP-0452 |
| 英文描述： | Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops |
| 中文描述： | 四端口旁路電路與光纖通道仲裁環(huán)路的CDR |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 273K |
| 代理商： | HDMP-0452 |
8
HDMP-0452 Output Jitter Characteristics
T
A
= 0
°
C to +70
°
C, V
CC
= 3.15 V to 3.45 V
Symbol
Parameter
RJ
Random Jitter at TO_NODE pins (1 sigma rms)
DJ
Deterministic Jitter at TO_NODE pins (pk-pk)
Units
ps
ps
Typ.
5
20
Max.
HDMP-0452 AC Electrical Specifications
T
A
= 0
°
C to +70
°
C, V
CC
= 3.15 V to 3.45 V
Symbol
Parameter
t
delay1
Total Loop Latency from FM_NODE[0] to TO_NODE[0]
t
delay2
Per Cell Latency from FM_NODE[4] to TO_NODE[0]
t
r,LVTTLin
Input LVTTL Rise Time Requirement, 0.8 V to 2.0 V
t
f,LVTTLin
Input LVTTL Fall Time Requirement, 2.0 V to 0.8 V
t
rs,HS_OUT
HS_OUT Single-Ended Rise Time, 20%-80%
t
fs,HS_OUT
HS_OUT Single-Ended Fall Time, 20%-80%
t
rd,HS_OUT
HS_OUT Differential Rise Time, 20%-80%
t
fd,HS_OUT
HS_OUT Differential Fall Time, 20%-80%
V
IP,HS_IN
HS_IN Input Peak-to-Peak Required Differential Voltage Range
V
OP,HS_OUT
HS_OUT Output Pk-Pk Diff. Voltage Range (Z0 = 75 Ohm, Fig. 9)
Units
ns
ns
ns
ns
ps
ps
ps
ps
mV
mV
Min.
Typ.
4.0
0.8
2
2
200
200
200
200
1200
1400
Max.
350
350
350
350
2000
2000
200
1100
HDMP-0452 Power Dissipation and Thermal Resistance
T
A
= 0
°
C to +70
°
C, V
CC
= 3.15 V to 3.45 V
Symbol
Parameter
P
D
Power Dissipation
Θ
jc
Thermal Resistance, Junction to Case
Units
mW
°
C/W
Typ.
660
7
Max.
950
Please refer to Figures 6 and 7 for jitter measurement setup information.
HDMP-0452 Locking Characteristics
T
A
= 0
°
C to +70
°
C, V
CC
= 3.15 V to 3.45 V
Parameter
Bit Sync Time (phase lock)
Frequency Lock at Powerup
Units
bits
μ
s
Max.
2500
500
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