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參數(shù)資料
| 型號： | HDMP-0452 |
| 英文描述： | Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops |
| 中文描述： | 四端口旁路電路與光纖通道仲裁環(huán)路的CDR |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 273K |
| 代理商： | HDMP-0452 |
3
Figure 1. Block diagram of HDMP-0452.
Table 1. Truth Table for CDR at Entry Configuration.
TO_LOOP
TO_NODE[4]
TO_NODE[3]
TO_NODE[2]
TO_NODE[1]
BYPASS[4]–
BYPASS[3]–
BYPASS[2]–
BYPASS[1]–
FM_LOOP
FM_NODE[1]
FM_NODE[2]
FM_LOOP
FM_NODE[1]
FM_NODE[2]
FM_LOOP
FM_NODE[1]
FM_NODE[2]
FM_LOOP
FM_NODE[1]
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
0
0
0
0
0
0
0
0
1
0
1
0
FM_NODE[2]
FM_NODE[3]
FM_NODE[3]
FM_NODE[2]
FM_NODE[3]
FM_NODE[3]
FM_NODE[2]
FM_LOOP
FM_NODE[1]
FM_NODE[1]
FM_LOOP
FM_NODE[1]
FM_LOOP
FM_LOOP
FM_LOOP
0
0
0
0
1
1
1
0
0
1
0
1
FM_NODE[3]
FM_NODE[3]
FM_NODE[4]
FM_NODE[3]
FM_NODE[3]
FM_LOOP
FM_NODE[2]
FM_NODE[2]
FM_LOOP
FM_LOOP
FM_NODE[1]
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
0
0
1
1
1
0
1
1
0
0
1
0
FM_NODE[4]
FM_NODE[4]
FM_NODE[4]
FM_NODE[4]
FM_NODE[1]
FM_NODE[2]
FM_NODE[2]
FM_NODE[3]
FM_NODE[1]
FM_NODE[2]
FM_NODE[2]
FM_LOOP
FM_NODE[1]
FM_LOOP
FM_NODE[1]
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
FM_LOOP
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
FM_NODE[4]
FM_NODE[4]
FM_NODE[4]
FM_NODE[3]
FM_NODE[3]
FM_NODE[3]
FM_NODE[1]
FM_NODE[2]
FM_NODE[2]
FM_NODE[1]
FM_LOOP
FM_NODE[1]
FM_LOOP
FM_LOOP
FM_LOOP
1
1
1
1
1
1
0
1
1
1
0
1
Note:
FM_LOOP = FM_NODE[0], TO_LOOP = TO_NODE[0], BYPASS[0]– = 1.
Table 2. Pin Connection Diagram to Achieve Desired CDR Location (see Figures 3, 4).
Hard Disks
A B C D
Connection to PBC Cells
1 2 3 4
CDR Position (x)
xA B C D
Cell Connected to Cable
0
A B C D
0 1 2 3
AxB C D
4
A B C D
4 0 1 2
A BxC D
3
A B C D
3 4 0 1
A B CxD
2
A B C D
2 3 4 0
A B C Dx
1
Note:
x denotes CDR position with respect to hard disks.
F
T
B
SD
CDR
REFCLK
CPLL
1
0
1
0
T
F
F
T
1
0
F
T
1
0
F
T
1
0
BLL
EQU
TTL
B
BLL
EQU
TTL
B
BLL
EQU
TTL
B
BLL
EQU
TTL
B
BLL
EQU
TTL
TTL
SD
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