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參數(shù)資料
| 型號(hào)： | GS8170S72 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb（256K x 72Bit）Synchronous SRAM(16M位（256K x 72位）同步靜態(tài)RAM) |
| 中文描述： | 16Mb的（256 × 72Bit）同步SRAM（1,600位（256 × 72位）同步靜態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 8/38頁(yè) |
| 文件大小： | 934K |
| 代理商： | GS8170S72 |
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Rev: 1.01 11/2000
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
8/38
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8170S18/36/72B-333/300/275/250
Common I/O Sigma RAM Family Mode Comparison—LW vs. DDR
Late Write---Pipelined Read
All address, data and control inputs (with the exception of G, PE2, PE3, and the mode pins, M2–M4) are synchronized to rising
clock edges. Read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new
address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any
one of the Enable inputs will deactivate the device.
It should be noted that ONLY deactivation of the RAM via E2 and/or E3
deactivates the Echo Clocks, CQ1–CQn.
Mode Selection Truth Table Standard
M2
0
M3
0
M4
0
Function
Analogous to...
Flow through Burst RAM
Flow through NBT SRAM & Flow
through Late Write SRAM
In This Data Sheet
Yes
Early Write, Flow through Read
0
0
1
Late Write, Flow through Read
Yes
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
RFU
DDR
n/a
No
Yes
Yes
Yes
n/a
Double Data Rate SRAM
Pipelined Burst RAM
Pipelined NBT SRAM
Pipelined Late Write SRAM
—
Early Write, Pipelined Read
Double Late Write, Pipelined Read
Late Write, Pipelined Read
RFU
DF
CQ
W
Control
X
X
W
CK
QD
Address
QA
DC
R
R
A
B
C
D
E
F
Double Data Rate Write---Double Data Rate Read
CQ
CK
Address
A
B
C
D
E
F
R
X
W
Control
R
X
W
D
Q
Q
D
D
Q
Q
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| GS8180D18 | 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫(xiě)模式靜態(tài)ΣRAM) |
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| GS8180S18 | 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫(xiě)模式靜態(tài)ΣRAM) |
| GS8180S09 | 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫(xiě)模式靜態(tài)ΣRAM) |
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參數(shù)描述 |
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| GS8171DW36AC-300I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays |
| GS8171DW36AC-350 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8171DW36AC-350I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209BGA - Trays |
| GS8171DW36AGC-250 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
| GS8171DW36AGC-300 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays |
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