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參數(shù)資料
| 型號： | GS8180S09 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| 中文描述： | 2MB的x 9Bit分離I / O西格瑪?shù)腄DR SRAM的（2米× 9位獨立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM） |
| 文件頁數(shù)： | 1/32頁 |
| 文件大?。?/td> | 853K |
| 代理商： | GS8180S09 |
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Rev: 1.01 11/2000
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
1/32
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180S09/18/36B-333/300/275/250
2M x 9, 1M x 18, 512K x 36
Separate I/O Sigma SDR SRAM
333 MHz
1.8 V V
DD
1.8 V and 1.5 V I/
209-Bump BGA
Commercial Temp
Industrial Temp
Σ
RAM
Features
Observes the Sigma RAM pinout standard
1.8 V +150/–100 mV core power supply
1.5 V or 1.8 V I/O supply
Pipelined read operation
Fully coherent read and write pipelines
Echo Clock outputs track data output drivers
ZQ mode pin for user-selectable output drive strength
2 user-programmable chip enable inputs for easy depth
expansion
IEEE 1149.1 JTAG-compatible Boundary Scan
209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
Pin compatible with future 32M, 64M and 128M devices
Sigma RAM Family Overview
The GS8180S09/18/36B are built in compliance with the
Sigma RAM pinout standard for Separate I/O synchronous
SRAMs. They are 18,874,368-bit (16Mb) SRAMs. These are
the first in a family of wide, very low voltage CMOS I/O
SRAMs designed to operate at the speeds needed to implement
economical high performance networking systems.
GSI's family of Common I/O
Σ
RAMs are offered in a number
of configurations that emulate other synchronous SRAMs,
such as Burst RAMs, NBT RAMs, Late Write, or Double Data
Rate (DDR) SRAMs. The logical differences between the
protocols employed by these RAMs hinge mainly on various
combinations of address bursting, output data registering, and
write cueing.
Σ
RAMs allow a user to implement the interface
protocol best suited to the task at hand.
Functional Description
Because a Sigma RAM is a synchronous device, address, data
Inputs, and read/ write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
Because the Separate I/O
Σ
RAM always transfers data in two
packets, A0 is internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next
transfer. Since the LSB is tied off internally, the address field
of a Separate I/O SDR
Σ
RAM is always one address pin less
than the advertised index depth (e.g., the 1M x 18 has a 512K
addressable index).
Single Data Rate (SDR) Separate I/O Sigma RAMs implement
a pipelined read and incorporate a rising-edge-triggered output
register. For read cycles, a pipelined SRAM’s output data is
temporarily stored by the edge-triggered output register during
the access cycle, and then released to the output drivers at the
next rising edge of clock.
GS818x18/36B
Σ
RAMs are implemented with GSI's high
performance CMOS technology and are packaged in a 209-
bump BGA.
- 333
3.0 ns
1.5 ns
Pipeline Mode
tKHKH
tKHQV
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Bottom View
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| GS8182D08BD-167 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.5NS 165FPBGA - Trays |
| GS8182D08BD-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.45NS 165FPBGA - Trays |
| GS8182D08BD-375 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.45NS 165FPBGA - Trays |
| GS8182D09BD-400 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 2M X 9 0.45NS 165FPBGA - Trays |
| GS8182D18BD-167 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 1MX18 0.5NS 165FPBGA - Trays |
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