參數(shù)資料
型號(hào)： GS8180S09
廠商： GSI TECHNOLOGY
英文描述： 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
中文描述： 2MB的x 9Bit分離I / O西格瑪?shù)腄DR SRAM的（2米× 9位獨(dú)立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM）
文件頁(yè)數(shù)： 25/32頁(yè)
文件大?。?/td> 853K
代理商： GS8180S09
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
25/32
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180S09/18/36B-333/300/275/250
When the TAP controller is placed in Capture-IR state, the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state, the Instruction Register is placed between TDI and TDO. In this state the
desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all
instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP
instruction set for this device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register, the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring con-
tents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not
harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAP’s input data
capture set-up plus hold time (tTS plus tTH ). The RAM’s clock inputs need not be paused for any other TAP operation except capturing the
I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the Boundary Scan Register between
Select DR
Capture DR
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
1
Select IR
Capture IR
0
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
Test Logic Reset
Run Test Idle
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
相關(guān)PDF資料
PDF描述
GS820322T-138 64K x 32 2M Synchronous Burst SRAM
GS82032Q-100 64K x 32 2M Synchronous Burst SRAM
GS82032Q-117 64K x 32 2M Synchronous Burst SRAM
GS82032T-66 64K x 32 2M Synchronous Burst SRAM
GS82032T-6I 64K x 32 2M Synchronous Burst SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8182D08BD-167 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.5NS 165FPBGA - Trays
GS8182D08BD-250 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.45NS 165FPBGA - Trays
GS8182D08BD-375 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.45NS 165FPBGA - Trays
GS8182D09BD-400 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 2M X 9 0.45NS 165FPBGA - Trays
GS8182D18BD-167 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 1MX18 0.5NS 165FPBGA - Trays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*