參數(shù)資料
型號(hào)： GS8180S09
廠商： GSI TECHNOLOGY
英文描述： 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
中文描述： 2MB的x 9Bit分離I / O西格瑪?shù)腄DR SRAM的（2米× 9位獨(dú)立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM）
文件頁(yè)數(shù)： 22/32頁(yè)
文件大?。?/td> 853K
代理商： GS8180S09
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
22/32
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180S09/18/36B-333/300/275/250
Timing Parameter Key - Control and Data In Timing
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface
standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Unlike
JTAG implementations that have been common among SRAM vendors for the last several years, this implementation does offer a
form of EXTEST, known as Clock Assisted EXTEST, reducing or eliminating the “hand coding” that has been required to
overcome the test program compiler errors caused by previous non-compliant implementations.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to
V
DD
. TDO should be left unconnected.
tKHnX
tnVKH
tAVKH
tKHAX
CK
A
A
B
C
E1, W,
E2, E3
D (Data In)
tKHDX
tDVKH
Note: tnVKH = tEVKH, tWVKH, etc. and tKHnX = tKHEX, tKHWX, etc.
DA0
DA1
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