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參數(shù)資料
| 型號(hào)： | GS8170S72 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb（256K x 72Bit）Synchronous SRAM(16M位（256K x 72位）同步靜態(tài)RAM) |
| 中文描述： | 16Mb的（256 × 72Bit）同步SRAM（1,600位（256 × 72位）同步靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 19/38頁 |
| 文件大?。?/td> | 934K |
| 代理商： | GS8170S72 |
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Rev: 1.01 11/2000
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
19/38
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8170S18/36/72B-333/300/275/250
Σ
RAM Synchronous Truth Table (G Low)
Previous
Cycle
Input
Type
E
1
E
ADV
W
Bx
Next
Cycle
Address
DQ
CQ
Notes
N/A
D
H
T
L
X
X
Deselect Cycle
None
Hi-Z
Q
—
Deselect
C
X
X
H
X
X
Deselect Cycle, Continue
Next
Hi-Z
Q
—
N/A
Dx
X
F
L
X
X
Bank Deselect Cycle
None
Hi-Z
Hi-Z
2
Bank
Deselect
C
X
X
H
X
X
Bank Deselect Cycle, Continue
Next
Hi-Z
Hi-Z
—
N/A
R
L
T
L
H
X
Read Cycle, Begin Burst
External
Q
Q
2
Read
C
X
X
H
X
X
Read Cycle, Continue Burst
Next
Q
Q
—
N/A
W
L
T
L
L
T
Write Cycle, Begin Burst
External
D
Q
2, 3
N/A
W
L
T
L
L
F
Non-Write Cycle, Begin Burst
External
Hi-Z
Q
2, 3, 4
Write
C
X
X
H
X
T
Write Cycle, Continue Burst
Next
D
Q
3, 5, 6
Write
C
X
X
H
X
F
Non-Write Cycle, Continue Burst
Next
Hi-Z
Q
3, 4, 5, 6
Notes:
1.
2.
3.
4.
5.
X = Don’t Care, H = High, L = Low
E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1
Bx = F (False) if all Byte Write Enable pins are high. Bx = T (True) if any one Byte Write Enable pin is low.
In NBT RAMs, an active cycle that starts with W = 0 but all Bx = False (high) is a Write Cycle (DQ’s Hi-Z) but no data is written.
The Byte Write Enable pins are only evaluated in a Continue cycle if the previous cycle was a Write.
Rev. 5
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