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參數(shù)資料
| 型號(hào)： | GS8170S72 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb（256K x 72Bit）Synchronous SRAM(16M位（256K x 72位）同步靜態(tài)RAM) |
| 中文描述： | 16Mb的（256 × 72Bit）同步SRAM（1,600位（256 × 72位）同步靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 10/38頁 |
| 文件大?。?/td> | 934K |
| 代理商： | GS8170S72 |
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Rev: 1.01 11/2000
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
10/38
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8170S18/36/72B-333/300/275/250
Pipelined Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2,
and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the
address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines
that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge
of clock the read data is allowed to propagate through the output register and onto the output pins.
Write Operations
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and
E3) are active and the write enable input signal (W) is asserted low.
Early Write
The classic “PB” (Pipelined Burst) SRAMs employed the “Early Write” protocol. This is to say that Address, Control (the write
command), and Data In are all required on the same clock edge.
/E
1
A
DQ
DD
QA
Write
Read
CK
Address
Read
Deselect
Deselect
F
XX
XX
E
D
Key
Hi-Z
Access
/W
CQ
Sigma Early Write with Pipelined Read
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| GS8171DW36AC-350 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
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