參數(shù)資料
型號: DS32512N+
廠商: Maxim Integrated Products
文件頁數(shù): 99/130頁
文件大?。?/td> 0K
描述: IC LIU DS3/E3/STS-1 12P 484-BGA
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 30
類型: 線路接口裝置(LIU)
規(guī)程: DS3
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 484-BGA
供應商設備封裝: 484-BGA(23x23)
包裝: 管件
DS32506/DS32508/DS32512
70 of 130
9.5 LIU Registers
ADDRESS
OFFSET
REGISTER
REGISTER DESCRIPTION
20h
Control Register 1
22h
Control Register 2
24h
Transmit Waveshaping Control Register 1
26h
Transmit Waveshaping Control Register 2
28h
Status Register
2Ah
Status Register Latched
2Ch
Status Register Interrupt Enable
2Eh
Receive Gain Level Register
Register Name:
LIU.CR1
Register Description:
LIU Control Register 1
Register Address:
n * 80h + 20h
Bit #
15
14
13
12
11
10
9
8
Name
JAD[1:0]
JAS[1:0]
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
TLBO
TOE
TTRE
TRESADJ[2:0]
Default
0
Bits 11, 10: Jitter Attenuator Depth (JAD[1:0]).
These bits select the jitter attenuator buffer depth. See Section
00 = 16 bits
01 = 32 bits
10 = 64 bits
11 = 128 bits
Bit 9, 8: Jitter Attenuator Select (JAS[1:0]).
These bits select the location of the jitter attenuator. See Section 8.4.
00 = Disabled
01 = Receive Path
10 = Transmit Path
11 = Transmit Path
Bit 5: Transmit LIU LBO (TLBO).
This bit is used to enable the transmit LBO circuit which causes the transmit
signal to be preattenuated to mimic the attenuation of approximately approximates about 225 feet of cable. This is
used to reduce near-end crosstalk when the cable lengths are short. This signal is only valid in DS3 and STS-1
modes. See Section 8.2.6.
0 = Disabled
1 = Enabled
Bit 4: Transmit Output Enable (TOE).
This bit enables the transmitter outputs (TXP and TXN). The transmitter
continues to operate internally when the transmitter is tri-stated. Only the line driver and driver monitor are
disabled. See Section 8.2.7. Note: This bit is ORed with the associated TOE input pin.
0 = TXP and TXN are high impedance
1 = TXP and TXN are driven
Bit 3: Transmit Termination Resistor Enable (TTRE).
This bit indicates when the transmitter internal termination
is enabled. See Section 8.2.8.
0 = Disabled, the transmitter is terminated externally
1 = Enabled, the transmitter is terminated internally
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