±5%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, T<" />
參數(shù)資料
型號: DS32512N+
廠商: Maxim Integrated Products
文件頁數(shù): 125/130頁
文件大?。?/td> 0K
描述: IC LIU DS3/E3/STS-1 12P 484-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 30
類型: 線路接口裝置(LIU)
規(guī)程: DS3
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-BGA(23x23)
包裝: 管件
DS32506/DS32508/DS32512
94 of 130
Table 11-3. Framer Interface Timing
(VDD18 = 1.8V
±5%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, TA = -40°C to +85°C.) (See Figure 11-1
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
(Notes 1, 2)
22.4
(Notes 2, 3)
29.1
RCLK/TCLK Clock Period
t1
(Notes 2, 4)
19.3
ns
RCLK Duty Cycle
t2/t, t3/t1
(Notes 5, 6)
45
50
55
%
TCLK Duty Cycle
t2/t, t3/t1
(Note 6)
30
70
%
LIU Reference Clock Duty Cycle
t2/t, t3/t1
(Notes 6, 7)
30
70
%
TPOS/TDAT, TNEG to TCLK Setup Time
t4
(Notes 6, 8)
3
ns
TPOS/TDAT, TNEG Hold Time
t5
(Notes 6, 8)
1
ns
RCLK to RPOS/RDAT, RNEG/RLCV
Value Change
t6
(Notes 5, 6, 9)
1
7
ns
RCLK Rise and Fall Time
t7
(Notes 6, 10 )
1
2
ns
TCLK Rise and Fall Time
t8
(Notes 5, 11)
2
ns
Note 1:
DS3 mode.
Note 2:
78MHz is the maximum instantaneous frequency for a gapped clock. The maximum average frequency is 45.094MHz for DS3,
34.643MHz for E3, and 52.255MHz for STS-1.
Note 3:
E3 mode.
Note 4:
STS-1 mode.
Note 5:
Outputs loaded with 25pF, measured at 50% threshold.
Note 6:
Not tested during production test.
Note 7:
The LIU reference clock must be a ±20ppm low-jitter clock. See Section 8.7.1 for more information on reference clocks.
Note 8:
When TCLKI = 0, TPOS/TDAT and TNEG are sampled on the rising edge of TCLK. When TCLKI = 1, TPOS/TDAT and TNEG are
sampled on the falling edge of TCLK.
Note 9:
When RCLKI = 0, RPOS/RDAT and RNEG/RLCV are updated on the falling edge of RCLK. When RCLKI = 1, RPOS/RDAT and
RNEG/RLCV are updated on the rising edge of RCLK.
Note 10:
Outputs loaded with 25pF, measured between VOL(MAX) and VOH(MIN).
Note 11:
Measured between VIL(MAX) and VIH(MIN).
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