參數(shù)資料
型號(hào): DS32512N+
廠商: Maxim Integrated Products
文件頁數(shù): 58/130頁
文件大小: 0K
描述: IC LIU DS3/E3/STS-1 12P 484-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 30
類型: 線路接口裝置(LIU)
規(guī)程: DS3
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-BGA(23x23)
包裝: 管件
DS32506/DS32508/DS32512
33 of 130
When
A BPV with the same polarity as the last BPV.
The third zero in an EXZ.
When
A BPV immediately preceded by a valid pulse (B, V).
A BPV with the same polarity as the last BPV.
In E3 mode, HDB3 decoding is performed, and RLCV is asserted during any RCLK cycle where the data on RDAT
causes one of the following code violations:
When
A BPV immediately preceded by a valid pulse (B, V) or by a valid pulse and a zero (B, 0, V).
A BPV with the same polarity as the last BPV.
The fourth zero in an EXZ.
When
A BPV with the same polarity as the last BPV.
In any cycle where RLCV is asserted to flag a BPV, the RDAT pin outputs a one. In any cycle where RLCV is
asserted to flag an EXZ, the RDAT pin outputs a zero. The state bit that tracks the polarity of the last BPV is
toggled on every BPV, whether part of a valid B3ZS/HDB3 codeword or not.
8.3.6.3
RCLK Inversion
The polarity of RCLK can be inverted to support a glueless interface to a variety of neighboring components.
Normally, data is output on the RPOS/RDAT and RNEG/RLCV pins on the falling edge of RCLK. To output data on
these pins on the rising edge of RCLK, pull the RCLKI pin high or set the PORT.INV:RCLKI configuration bit.
8.3.6.4
Receiver Output Disable
The RCLK, RPOS/RDAT and RNEG/RLCV pins can be disabled (put in a high-impedance state) to support
protection switching and redundant-LIU applications. This capability supports system configurations where two or
more LIUs are wire-ORed together and a system processor selects one to be active. To disable these pins, set the
PORT.CR2:ROD configuration bit.
8.3.7 Power-Down
To minimize power consumption when the receiver is not being used, assert the RPD pin (all ports) or the
PORT.CR1:RPD configuration bit (per port). When the receiver is powered down, the RCLK, RPOS/RDAT, and
RNEG/RLCV pins are disabled (high impedance). In addition, the RXP and RXN pins become high impedance.
8.3.8 Input Failure Detection
The LIU receiver can detect opens and shorts on the RXP and RXN differential inputs. By default, the receiver
detects the following problems, collectively labeled type 1 failures: open RXP connection, open RXN connection,
common-mode RXP/RXN short to VDD, and common-mode RXP/RXN short to VSS. Type 1 failures are reported on
LIU.SR:RFAIL1. RFAIL1 is cleared when activity is detected on both RXP and RXN.
If LIU.CR2:RFL2E = 1, the receiver also detects a type 2 failure, which is an open or high-impedance path between
RXP and RXN. In a board with the external components shown in Figure 4-1 or Figure 4-2, the receive transformer
normally presents a low-impedance path between RXP and RXN. To detect a type 2 failure, the receiver connects
an 40
μA DC current source to RXP and measures the impedance between RXP and RXN. When this impedance is
greater than about 5k
Ω the receiver declares a type 2 failure on LIU.SR:RFAIL2. When the type 2 failure detection
circuitry is enabled, internal termination must be disabled (LIU.CR2:RTRE = 0) and external termination must not
be present or a type 2 failure will not be detected because the impedance of the termination is below the type 2
failure threshold.
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