參數(shù)資料
型號: DS32512N+
廠商: Maxim Integrated Products
文件頁數(shù): 63/130頁
文件大?。?/td> 0K
描述: IC LIU DS3/E3/STS-1 12P 484-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 30
類型: 線路接口裝置(LIU)
規(guī)程: DS3
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-BGA(23x23)
包裝: 管件
DS32506/DS32508/DS32512
38 of 130
8.5.2.1
Receive PRBS Synchronization
PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The
receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and
then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern. If
at least six incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern
resynchronization is initiated. Automatic pattern resynchronization can be disabled by setting BERT.CR:APRD = 1.
Pattern resynchronization can also be initiated manually by a zero-to-one transition of the Manual Pattern
Resynchronization bit (BERT.CR:MPR). The incoming data stream can be inverted before comparison with the
receive pattern generator by setting BERT.CR:RPIC. See Figure 8-8 for the PRBS synchronization diagram.
Figure 8-8. PRBS Synchronization State Diagram
Sync
Load
Verify
1 bit error
32 bits loaded
32
bit
s
w
ith
ou
t e
rr
or
s
6
of
64
bit
s
w
ith
err
ors
8.5.2.2
Receive Repetitive Pattern Synchronization
Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern.
The receive pattern generator is synchronized by searching each incoming data stream bit position for the
repetitive pattern, and then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match
the incoming pattern. If at least six incoming bits in the current 64-bit window do not match the receive PRBS
pattern generator, automatic pattern resynchronization is initiated. Automatic pattern re-synchronization can be
disabled by setting BERT.CR:APRD = 1. Pattern resynchronization can also be initiated manually by a zero-to-one
transition of the Manual Pattern Resynchronization bit (BERT.CR:MPR). The incoming data stream can be inverted
before comparison with the receive pattern generator by setting BERT.CR:RPIC.
See Figure 8-9 for the repetitive pattern synchronization state diagram.
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