參數(shù)資料
型號： DS3131
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： Telecom IC:Other
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 8/174頁
文件大小： 1261K
代理商： DS3131
DS3131
105 of 174
9.3.2 Packet Descriptors
A contiguous section of up to 65,536 quad dwords that make up the transmit packet descriptors resides in
main memory. The transmit packet descriptors are aligned on a quad-dword basis and can be placed
anywhere in the 32-bit address space through the transmit descriptor base address (Table 9-I). A data
buffer is associated with each descriptor. The data buffer can be up to 8191 Bytes long and must be a
contiguous section of main memory. The host informs the DMA of data buffers’ actual sizes through the
byte count field that resides in the packet descriptor.
If an outgoing packet requires more space than the data buffer allows, then packet descriptors are link-
listed together by the host to provide a chain of data buffers. Figure 9-15 shows an example of how three
descriptors were linked together for an incoming packet on HDLC channel 7. Channel 3 only required a
single data buffer and thus only one packet descriptor was used. Figure 9-10 shows a similar example for
channels 5 and 1.
Packet descriptors can be either pending (i.e., queued up by the host and ready for transmission by the
DMA) or completed (i.e., have been transmitted by the DMA and are available for processing by the
host). Pending-packet descriptors are pointed to by the pending-queue descriptors and completed packet
descriptors are pointed to by the done-queue descriptors.
Table 9-I. Transmit Descriptor Address Storage
REGISTER
NAME
ADDRESS
Transmit Descriptor Base Address 0 (lower word)
TDBA0
0850h
Transmit Descriptor Base Address 1 (upper word)
TDBA1
0854h
Figure 9-15. Transmit Descriptor Example
CH 5 Single Sent Buffer Descriptor
Base + 00h
CH 7 1st Queued Buffer Descriptor
Base + 10h
Base + 20h
CH 7 Sent 1st Buffer Descriptor
Base + 30h
Free Descriptor
Base + 40h
Base + 50h
Free Descriptor
Base + 60h
Base + 70h
CH 7 Last Sent Buffer Descriptor
Base + 80h
Free Descriptor
Base + FFFD0h
Free Descriptor
Base + FFFF0h
CH 3 Single Queued Buffer Desc.
CH 7 2nd Queued Buffer Descriptor
CH 7 Last Queued Buffer Descriptor
Pending-Queue Descriptor Address
Done-Queue Descriptor Pointer
Maximum of 65,536 Descriptors
相關(guān)PDF資料
PDF描述
DS3134 DATACOM, FRAMER, PBGA256
DS3150QN DATACOM, PCM TRANSCEIVER, PQCC28
DS3150Q DATACOM, PCM TRANSCEIVER, PQCC28
DS3150TN DATACOM, PCM TRANSCEIVER, PDIP48
DS3150T DATACOM, PCM TRANSCEIVER, PQFP48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3131DK 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube
DS3134 功能描述:IC CTRLR HDLC CHATEAU 256-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
DS-313PIN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Miscellaneous
DS-313-PIN 功能描述:信號調(diào)節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel
DS31400 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*