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| 型號(hào)： | DS3131 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Telecom IC:Other |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁(yè)數(shù)： | 134/174頁(yè) |
| 文件大?。?/td> | 1261K |
| 代理商： | DS3131 |
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DS3131
62 of 174
Bit 1/Receive Maximum Octet Length-Detection Enable (ROLD). When this bit is set low, the HDLC
controller does not check to see if the octet length of the received packets exceeds the count loaded into the receive
HDLC packet length (RHPL) register. When this bit is set high, the HDLC controller checks to see if the octet
length of the received packets exceeds the count loaded into the RHPL register. When an incoming packet exceeds
the maximum length, the packet is aborted and the remainder is discarded. This bit is ignored if the HDLC channel
is set to transparent mode (RTRANS = 1).
0 = octet length detection disabled
1 = octet length detection enabled
Bits 2, 3/Receive CRC Selection (RCRC0/RCRC1). These two bits are ignored if the HDLC channel is set into
transparent mode (RTRANS = 1).
RCRC1
RCRC0
ACTION
0
No CRC verification performed
0
1
16-bit CRC (CCITT/ITU Q.921)
1
0
32-bit CRC
1
Illegal state
Bit 4/Receive Invert Data Enable (RID). When this bit is set low, the incoming HDLC packets are not inverted
before processing. When this bit is set high, the HDLC controller inverts all the data (flags, information fields, and
FCS) before processing the data. The data is not reinverted before passing to the FIFO.
0 = do not invert data
1 = invert all data (including flags and FCS)
Bit 5/Receive Bit Flip (RBF). When this bit is set low, the HDLC controller places the first HDLC bit received in
the lowest bit position of the PCI bus bytes (i.e., PAD[0], PAD[8], PAD[16], PAD[24]). When this bit is set high,
the HDLC controller places the first HDLC bit received in the highest bit position of the PCI bus bytes (i.e.,
PAD[7], PAD[15], PAD[23], PAD[31]).
0 = the first HDLC bit received is placed in the lowest bit position of the bytes on the PCI bus
1 = the first HDLC bit received is placed in the highest bit position of the bytes on the PCI bus
Bit 6/Receive CRC Strip Enable (RCS). When this bit is set high, the FCS is not transferred through to the PCI
bus. When this bit is set low, the HDLC controller includes the 2-Byte FCS (16-bit) or 4-Byte FCS (32-bit) in the
data that it transfers to the PCI bus. This bit is ignored if the HDLC channel is set into transparent mode
(RTRANS = 1).
0 = send FCS to the PCI bus
1 = do not send the FCS to the PCI bus
Bit 7/Receive Abort Disable (RABTD). When this bit is set low, the HDLC controller examines the incoming
data stream for the abort sequence, which is seven or more consecutive 1s. When this bit is set high, the incoming
data stream is not examined for the abort sequence, and, if an incoming abort sequence is received, no action is
taken. This bit is ignored when the HDLC controller is configured in the transparent mode (RTRANS = 1).
0 = abort detection enabled
1 = abort detection disabled
Bit 8/Receive Zero Destuffing Disable (RZDD). When this bit is set low, the HDLC controller zero destuffs the
incoming data stream. When this bit is set high, the HDLC controller does not zero destuff the incoming data
stream. This bit is ignored when the HDLC controller is configured in the transparent mode (RTRANS = 1).
0 = zero destuffer enabled
1 = zero destuffer disabled
Bit 9/Receive Port Enable (RPEN). When this bit is set low, the receive port is disabled. When this bit is set
high, the receive port is enabled. By default, this bit defaults the port in an off state (RPEN = 0).
0 = port disabled (default)
1 = port enabled
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150TN | DATACOM, PCM TRANSCEIVER, PDIP48 |
| DS3150T | DATACOM, PCM TRANSCEIVER, PQFP48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3131DK | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS3134 | 功能描述:IC CTRLR HDLC CHATEAU 256-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| DS-313PIN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Miscellaneous |
| DS-313-PIN | 功能描述:信號(hào)調(diào)節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel |
| DS31400 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter |
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