參數(shù)資料
型號: DS3131
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Telecom IC:Other
英文描述: SPECIALTY TELECOM CIRCUIT, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 29/174頁
文件大?。?/td> 1261K
代理商: DS3131
DS3131
124 of 174
10.1.3 PCI Bus Arbitration
The PCI bus can be arbitrated as shown in Figure 10-4. The initiator requests bus access by asserting
PREQ. A central arbiter grants the access some time later by asserting PGNT. Once the bus has been
granted, the initiator waits until both PIRDY and PFRAME are deasserted (i.e., an idle cycle) before
acquiring the bus and beginning the transaction. As shown in Figure 10-3, the bus was still being used
when it was granted and the device had to wait until clock cycle #6 before it acquired the bus and began
the transaction. The arbiter can deassert PGNT at any time and the initiator must relinquish the bus after
the current transfer is complete, which can be limited by the latency timer.
Figure 10-4. PCI Bus Arbitration Signaling Protocol
10.1.4
PCI Initiator Abort
If a target fails to respond to an initiator by asserting PDEVSEL and PTRDY within 5 clock cycles, then
the initiator aborts the transaction by deasserting PFRAME and then, one clock later, by deasserting
PIDRY (Figure 10-5). If such a scenario occurs, it is reported through the master abort status bit in the
PCI command/status configuration register (Section 10.2).
Figure 10-5. PCI Initiator Abort
123456
78910
PCLK
PREQ
PGNT
PFRAME
Bus is Relinquished
Bus is Acquired
Wait for
PGNT Asserted
and then
PFRAME and
PIRDY Deasserted
12345678910
PCLK
PFRAME
PIRDY
PTRDY
PDEVSEL
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