參數(shù)資料
型號： DS3131
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： Telecom IC:Other
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 11/174頁
文件大小： 1261K
代理商： DS3131
DS3131
108 of 174
The transmit DMA reads from the transmit pending-queue descriptor circular queue which data buffers
and their associated descriptors are ready for transmission. A set of internal addresses within the device
that are accessed by both the host and the DMA keep track of the circular queue addresses in the transmit
pending queue. On initialization, the host configures all of the registers shown in Table 9-J. After
initialization, the DMA only writes to (changes) the read pointers and the host only writes to the write
pointers.
Empty Case
The transmit pending queue is considered empty when the read and write pointers are identical.
Transmit Pending-Queue Empty State
empty descriptor
read pointer >
empty descriptor
< write pointer
empty descriptor
Full Case
The transmit pending queue is considered full when the read pointer is ahead of the write pointer by one
descriptor. Therefore, one descriptor must always remain empty.
Transmit Pending-Queue Full State
valid descriptor
empty descriptor
< write pointer
read pointer >
valid descriptor
Table 9-J. Transmit Pending-Queue Internal Address Storage
REGISTER
NAME
ADDRESS
Transmit Pending-Queue Base Address 0 (lower word)
TPQBA0
0800h
Transmit Pending-Queue Base Address 1 (upper word)
TPQBA1
0804h
Transmit Pending-Queue Host Write Pointer
TPQWP
080Ch
Transmit Pending-Queue DMA Read Pointer
TPQRP
0810h
Transmit Pending-Queue End Address
TPQEA
0808h
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相關代理商/技術參數(shù)
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