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參數(shù)資料
| 型號(hào)： | AX88196BLF |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller with MII Interface |
| 中文描述： | 低引腳數(shù)不符合信息產(chǎn)業(yè)部的PCI接口16位產(chǎn)品個(gè)10/100M快速以太網(wǎng)控制器 |
| 文件頁(yè)數(shù)： | 74/86頁(yè) |
| 文件大?。?/td> | 551K |
| 代理商： | AX88196BLF |
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ASIX ELECTRONICS CORPORATION
74
AX88196BLF
7.4.5 Burst Reads Access Timing
Burst read access is enabled when set FIFO_SEL(SA5) is driven high during a read access. This is normally
accomplished by connecting the FIFO_SEL(SA5) signal to a high-order address line. This mode is useful when
the host processor must increment its address when accessing the AX88196B.
In this mode, performance is improved by allowing an unlimited number of back-to-back WORDS read cycles.
AX88196B base on SA0 or SA1 address toggles to identify WORD access cycle time. Host can set burst cycle
base on SA0 or SA1 toggle by BCB1 (CR page3 Offset 0Dh).
Tdoff
Tdoh
Tadv
Tadv
Tadv
Tdv
Tdon
Trdh
Tah
Tasu
Tacyc
Tacyc
Tacyc
FIFO_SEL(SA5)
SA1 or SA0
CSn, RDn
SD[15:0]
Symbol
Tasu
Tah
Tdv
Description
Min
0
0
-
Typ.
-
-
-
Max
-
-
33*
1
35*
2
33*
1
35*
2
-
-
7
Units
ns
ns
ns
ADDRESS SETUP TIME
ADDRESS HOLD TIME
DATA VALID TIME FROM RDn
Tadv
DATA VALID TIME FROM ADDRESS
ns
Tdoh
Trdh
Tacyc
Tdon
Tdoff
DATA OUTPUT HOLD TIME
RDn HI REQUIRE TIME
READ CYCLE TIME
DATA BUFFER TURN ON
DATA BUFFER TURN OFF
0
13
48
0
-
-
ns
ns
ns
ns
ns
*
1
: Base on SD bus output load 25pF
*
2
: Base on SD bus output load 50pF
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AX88196L | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM |
| AX88613 | 制造商:ASIX 制造商全稱(chēng):ASIX 功能描述:ASIX Multi-Port Ethernet Controller |
| AX88615 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:5-Port 10/100BASE Ethernet Switch |
| AX88615P | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:5-Port 10/100BASE Ethernet Switch |
| AX8863T | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Low-Dropout, 120mA Linear Regulators |
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