參數(shù)資料
型號(hào)： AX88196BLF
廠商： ASIX Electronics Corporation
英文描述： Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller with MII Interface
中文描述： 低引腳數(shù)不符合信息產(chǎn)業(yè)部的PCI接口16位產(chǎn)品個(gè)10/100M快速以太網(wǎng)控制器
文件頁(yè)數(shù)： 13/86頁(yè)
文件大?。?/td> 551K
代理商： AX88196BLF
ASIX ELECTRONICS CORPORATION
13
AX88196BLF
4.0 Basic Operation
4.1 Receiver Filtering
The address filtering logic compares the Destination Address Field (first 6 bytes of the received packet) to the
Physical address registers stored in the Address Register Array. If any one of the six bytes does not match the
pre-programmed physical address, the Protocol Control Logic rejects the packet. This is for unicast address filtering.
All multicast destination addresses are filtered using a hashing algorithm. (See following description.) If the
multicast address indexes a bit that has been set in the filter bit array of the Multicast Address Register Array the
packet is accepted, otherwise the Protocol Control Logic rejects it. Each destination address is also checked for all
1’s, which is the reserved broadcast address.
4.1.1 Unicast Address Match Filter
The physical address registers are used to compare the destination address of incoming packets for rejecting or
accepting packets. Comparisons are performed on a byte wide basis. The bit assignment shown below relates the
sequence in PAR0-PAR5 to the bit sequence of the received packet.
D7
D6
D5
D4
PAR0
DA7
DA6
DA5
DA4
PAR1
DA15
DA14
DA13
DA12
PAR2
DA23
DA22
DA21
DA20
PAR3
DA31
DA30
DA29
DA28
PAR4
DA39
DA38
DA37
DA36
PAR5
DA47
DA46
DA45
DA44
Note:
The bit sequence of the received packet is DA0, DA1, … DA7, DA8 ….
4.1.2 Multicast Address Match Filter
The Multicast Address Registers provide filtering of multicast addresses hashed by the CRC logic. All destination
addresses are fed through the 32 bits CRC generation logic and as the last bit of the destination address enters the
CRC, the 6 most significant bits of the CRC generator are latched. These 6 bits are then decoded by a 1 of 64 decode
to index a unique filter bit (FB0-63) in the Multicast Address Registers. If the filter bit selected is set, the multicast
packet is accepted. The system designer would use a program to determine which filter bits to set in the multicast
registers. All multicast filter bits that correspond to Multicast Address Registers accepted by the node are then set to
one. To accept all multicast packets all of the registers are set to all ones.
D7
D6
D5
D4
MAR0
FB7
FB6
FB5
FB4
MAR1
FB15
FB14
FB13
FB12
MAR2
FB23
FB22
FB21
FB20
MAR3
FB31
FB30
FB29
FB28
MAR4
FB39
FB38
FB37
FB36
MAR5
FB47
FB46
FB45
FB44
MAR6
FB55
FB54
FB53
FB52
MAR7
FB63
FB62
FB61
FB60
D3
DA3
DA11
DA19
DA27
DA35
DA43
D2
DA2
DA10
DA18
DA26
DA34
DA42
D1
DA1
DA9
DA17
DA25
DA33
DA41
D0
DA0
DA8
DA16
DA24
DA32
DA40
D3
FB3
FB11
FB19
FB27
FB35
FB43
FB51
FB59
D2
FB2
FB10
FB18
FB26
FB34
FB42
FB50
FB58
D1
FB1
FB9
FB17
FB25
FB33
FB41
FB49
FB57
D0
FB0
FB8
FB16
FB24
FB32
FB40
FB48
FB56
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