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參數(shù)資料
| 型號(hào)： | AX88196BLF |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller with MII Interface |
| 中文描述： | 低引腳數(shù)不符合信息產(chǎn)業(yè)部的PCI接口16位產(chǎn)品個(gè)10/100M快速以太網(wǎng)控制器 |
| 文件頁(yè)數(shù)： | 15/86頁(yè) |
| 文件大小： | 551K |
| 代理商： | AX88196BLF |
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ASIX ELECTRONICS CORPORATION
15
AX88196BLF
4.1.5 Aggregate Address Filter with Receive Configuration Setup
The final address filter decision depends on the destination address types, identified by the above 4 address match
filters, and the setup of parameters of Receive Configuration Register.
Definitions of address match filter result are as following:
Signal
Value
Description
Phy
=1
Unicast Address Match
=0
Unicast Address not Match
Mul
=1
Multicast Address Match
=0
Multicast Address not Match
Bro
=1
Broadcast Address Match
=0
Broadcast Address not Match
VID
=1
VLAN ID Match
=0
VLAN ID not Match
AGG
=1
Aggregate Address Match
=0
Aggregate Address not Match
The meaning of AB, AM and PRO signals, please refer to “Receive Configuration Register” RCR (offset 0Ch)
The meaning of VLANE signal, Please refer to “MAC Configure Register” MCR (offset 1Bh)
Aggregate Address Filter function will be:
AB
Bro
/Mul
/Bro
PRO
Mul
/Bro
AM
Phy
VLANE
VID
AGG
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