參數(shù)資料
型號: AX88196BLF
廠商: ASIX Electronics Corporation
英文描述: Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller with MII Interface
中文描述: 低引腳數(shù)不符合信息產(chǎn)業(yè)部的PCI接口16位產(chǎn)品個10/100M快速以太網(wǎng)控制器
文件頁數(shù): 6/86頁
文件大?。?/td> 551K
代理商: AX88196BLF
ASIX ELECTRONICS CORPORATION
6
AX88196BLF
2.0 Signal Description
The following abbreviations are used in AX88196B pinout tables:
All pin names with the “n” suffix are low-active signals.
I Input 1.8V
O Output 1.8V
I5 Input 3.3V with 5V tolerant
O5 Output 3.3V with 5V tolerant
T5 Tri-state with 5V tolerant
B5 Bi-directional I/O, 3.3V with 5V tolerant
4m 4mA driving strength
8m 8mA driving strength
S Schmitt trigger
PU Internal Pull Up 75Kohm
PD Internal Pull Down 75kohm
P Power Pin
A Analog
2.1 Local CPU Bus Interface Signals Group
Signal
Type
Pin No.
SA[4:0]
SA[5] or
FIFO_SEL
Description
I5
74, 75, 76, 77, 79
System Address: Signals SA[4:0] are address bus input lines.
Used to select internal CSR’s.
System Address or FIFO Select: When driven high, all accesses
to the AX88196B are to the RX or TX data buffer FIFO (DP).
AX88196B supports two kinds of Data Port for
receiving/transmitting packets from/to AX88196B. One is the
PIO Data Port (offset 10h); the other one is the SRAM-like Data
Port (e.g. offset 800h ~ FFFh for Samsung2440 processor as
described in Appendix A4 of AX88196B datasheet). The
SRAM-like Data Port address range depends on which address
line of host processor is being connected to the address line
SA5/FIFO_SEL of AX88196B.
Software on host CPU can issue Single Data Read/Write
command to both PIO Data Port and SRAM-like Data Port.
However, to use Burst Data Read/Write commands, one has to
use SRAM-like Data Port, which requires SA5/FIFO_SEL (pin
45) of AX88196B connecting to an upper address line of host
CPU. Our reference schematic has SA5/FIFO_SEL pin
connected to upper address line for supporting Burst Data
Read/Write commands.
System Data Bus: Signals SD[15:0] constitute the bi-directional
data bus.
I5/PD
67
SD[15:0]
B5/8m
43, 44, 45, 46, 47, 48,
49, 50, 52, 53, 54, 55,
57, 58, 59, 60
37
IRQ
O5/T5/8m
Programmable Interrupt request. Programmable polarity, source
and buffer types.
Can be configure by EEPROM auto-loader or BTCR (offset 15h)
Chip Select: Active low.
Read: Active low strobe to indicate a read cycle.
Write: Active low strobe to indicate a write cycle. This signal also
used to wakeup the AX88196B when it is in reduced power state.
16 Bit Port: For ISA bus used. The IOIS16n is asserted when the
address at the range corresponds to an I/O address to which the
chip responds, and the I/O port addressed is capable of 16-bit
access.
Address Enable: When 186, ISA mode, this signal is active low
to access AX88196B.
PSEN: When 51 modes, this signal is active high to access
AX88196B.
CSn
RDn
WRn
IOIS16n
I5
I5
I5
83
85
86
T5/8m
87
AEN or PSEN
I5
81
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