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參數(shù)資料
| 型號(hào)： | AX88196BLF |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller with MII Interface |
| 中文描述： | 低引腳數(shù)不符合信息產(chǎn)業(yè)部的PCI接口16位產(chǎn)品個(gè)10/100M快速以太網(wǎng)控制器 |
| 文件頁(yè)數(shù)： | 54/86頁(yè) |
| 文件大小： | 551K |
| 代理商： | AX88196BLF |
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ASIX ELECTRONICS CORPORATION
54
AX88196BLF
5.1.73 VLAN ID 0 Register (VIDR0)
Offset 1CH (Write)
Field
Name
Description
7:0
VIDR0
VLAN ID [7:0]
5.1.74 Current TX End Page Register (CTEPR)
Offset 1CH (Read)
Field
Name
Description
(Default = 00h)
7
TXCQF
TX Command Queue full
When set, indicate the TX Command queue was full. Host must check this status before
queuing next transmit page and byte count.
6:0
CTEPR
AX88196B will update CTEPR (current TX end page)
After every transmitting completed without collision.
It is for Host to conform how many free page can reuse for next transmitting.
The value is from 40h to 7Fh. It will be 00h when reset or STP.
5.1.75 VLAN ID 1 Register (VIDR1)
Offset 1DH (Write)
Field
Name
Description
7:5
PRI
Frame’s priority
4
CFI
Canonical Address Frame Indicator
3:0
VIDR1
VLAN ID [11:8]
5.1.76 Big-Endian Register (BER)
Offset 1EH (Write)
Field
Name
Description
(Default = 00h)
7:0
-
All zero, (Default): little-endian
If not all zero means set data byte order as big-endian mode.
Note: This mode can be used by 32-bit big-endian mode of processors operating with an
external 16-bit bus only.
5.1.77 Host Wake Up Register (HWUR)
Offset 1FH (Write)
Field
Name
Description
7:1
-
Reserved
0
HWAKE
(SC)
wake up.
Host write one to wake up AX88196B from D2 power saving. It will be auto clear when
5.1.78 Software Reset
Offset 1FH (Read)
Field
Name
7:0
-
Description
Don’t care this read value.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AX88196L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM |
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| AX88615P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-Port 10/100BASE Ethernet Switch |
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