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參數(shù)資料
| 型號： | ADV7321KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 66/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VID ENC 6-12BIT DAC'S 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | EVD，DVD，SD/PS/HDTV |
| 電壓 - 電源，模擬： | 2.5V |
| 電壓 - 電源，數(shù)字： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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ADV7320/ADV7321
Rev. A | Page 69 of 88
APPENDIX 3—SD CLOSED CAPTIONING
[Subaddresses 0x51 to 0x54]
The ADV7320/ADV7321 support closed captioning conforming
to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the blanked
active line time of Line 21 of the odd fields and Line 284 of the
even fields.
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency- and phase-locked to the caption data. After the
clock run-in signal, the blanking level is held for two data bits
and is followed by a Logic 1 start bit. Sixteen bits of data follow
the start bit. These consist of two 8-bit bytes, seven data bits,
and one odd parity bit. The data for these bytes is stored in the
SD closed captioning registers [Addresses 0x53 to 0x54].
The ADV7320/ADV7321 also support the extended closed
captioning operation, which is active during even fields and
encoded on Scan Line 284. The data for this operation is stored
in the SD closed captioning registers [Addresses 0x51 to 0x52].
All clock run-in signals and timing to support closed captioning
on Lines 21 and 284 are generated automatically by the ADV7320/
ADV7321. All pixels inputs are ignored during Lines 21 and 284
if closed captioning is enabled.
FCC Code of Federal Regulations (CFR) 47 section 15.119 and
EIA608 describe the closed captioning information for Line 21
and Line 284.
The ADV7320/ADV7321 use a single-buffering method. This
means that the closed captioning buffer is only 1 byte deep;
therefore, there is no frame delay in outputting the closed
captioning data, unlike other 2-byte-deep buffering systems.
The data must be loaded one line before it is output on Line 21
and Line 284. A typical implementation of this method is to use
VSYNC to interrupt a microprocessor, which in turn loads the
new data (2 bytes) in every field. If no new data is required for
transmission, 0s must be inserted in both data registers; this is
called nulling. It is also important to load control codes, all of
which are double bytes, on Line 21, or a TV will not recognize
them. If there is a message such as “Hello World” that has an
odd number of characters, it is important to add a blank
character at the end so that the end-of-caption, 2-byte control
code lands in the same field.
D0–D6
10.5
± 0.25μs
12.91
μs
7CYCLES OF
0.5035MHz
CLOCK RUN-IN
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
50 IRE
40 IRE
10.003
μs
27.382
μs
33.764
μ s
BYTE 1
BYTE 0
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
S
T
A
R
T
P
A
R
I
T
Y
P
A
R
I
T
Y
05067-098
Figure 98. Closed Captioning Waveform, NTSC
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